Efficient run-time task allocation in reconfigurable multiprocessor System-on-Chip with Network-on-Chip

Suganya, K.; Nagarajan, Vijay

doi:10.1109/icccet.2011.5762458

Cited by 2 publications

(2 citation statements)

References 5 publications

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“…An Integer Linear Programming (ILP) approach is described [15] with Simulated Annealing with Timing Adjustment (SA-TA) heuristic to accelerate the optimization process. System on a programmable chip design for a multicore embedded system is proposed in [16]. The optimization criteria of the task allocator is made to adapt itself according to the relative scarcity of different types of resources, by dynamically adjusting a set of parameters at run time is described in [17].…”

Section: Related Workmentioning

confidence: 99%

Minimal Task Allocation in Multiprocessors using improved next-fit for RM scheduling

B¹,

Pillai²

2012

IJCA

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Task-processor allocation in multiprocessors can be accomplished efficiently for reducing the required number of processors for the given task set, accounting reduced power consumption with maximum processor utilization. This work is based on next fit algorithm using Rate Monotonic Algorithm (RMA) for a fixed priority system. The work proposes a minimal task allocation algorithm for multiprocessor environment. The proposed method reduces the number of processors required for a given task set using improved next fit algorithm and the same has been evaluated and tested. The proposed algorithm gives better results when there is large number of tasks in the system.

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Section: Related Workmentioning

confidence: 99%

Minimal Task Allocation in Multiprocessors using improved next-fit for RM scheduling

B¹,

Pillai²

2012

IJCA

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“…System-on-chip (SoC) is a system, consisting of a processing core as well as analog and digital circuits built on a single silicon chip. The circuits and the processor are interconnected by means of buses [2]. While, the number of processors on a SoC is increased, bus arbitration and bandwidth became the bottleneck.…”

Section: Introductionmentioning

confidence: 99%

Efficient Router Architecture design on FPGA for Torus based Network on Chip

Venugopal¹,

Arulanandasamy²,

Ramachandran³

2012

IJCA

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Network-on-Chip (NoC) is an emerging technology for interconnecting multiple cores on a single silicon chip. In NoCs, hardware modules such as CPU cores, memories and I/O controllers are interconnected through a suitable network topology for sharing the data. This paper proposes a Multiprocessor NoC (MPNOC) based on torus network topology using wormhole switching. This NoC architecture consists of heterogeneous processing elements and core interfacing devices. We show that the proposed novel router architecture composed of small crossbar switch with Virtual channel memory requires less logical resources and reduce the routing complexity in wormhole switching in torus which provide high throughput performance evaluation and FPGA implementation of the system results are also given.

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Efficient run-time task allocation in reconfigurable multiprocessor System-on-Chip with Network-on-Chip

Cited by 2 publications

References 5 publications

Minimal Task Allocation in Multiprocessors using improved next-fit for RM scheduling

Minimal Task Allocation in Multiprocessors using improved next-fit for RM scheduling

Efficient Router Architecture design on FPGA for Torus based Network on Chip

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