Efficient Router Bypass via Hybrid Flow Control

Perez, Ivan; Vallejo, Enrique; Beivide, Ramón

doi:10.1109/nocarc.2018.8541147

Cited by 10 publications

(9 citation statements)

References 12 publications

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“…The current paper reviews and extends the work originally announced in [10]. This research proposes Non-Empty Buffer Bypass (NEBB), a novel approach for the use of the bypass that increases its utilization and effectiveness.…”

Section: Introductionmentioning

confidence: 88%

Efficient bypass in mesh and torus NoCs

Perez

Vallejo

Beivide

2020

Journal of Systems Architecture

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Minimizing latency and power are key goals in the design of NoC routers. Different proposals combine lookahead routing and router bypass to skip the arbitration and buffering, reducing router delay. However, the conditions to use them requires completely empty buffers in the intermediate routers. This restricts the amount of flits that use the bypass pipeline especially at medium and high loads, increasing latency and power. This paper presents NEBB, Non-Empty Buffer Bypass, a mechanism that allows to bypass flits even if the buffers to bypass are not empty. The mechanism applies to wormhole and virtual-cut-through, each of them with different advantages. NEBB-Hybrid is proposed to employ the best flow control in each situation. The mechanism is extended to torus topologies, using FBFC and shared buffers. The proposals have been evaluated using Booksim, showing up to 75% reduction of the buffered flits for single-flit packets, which translates into latency and dynamic power reductions of up to 30% and 23% respectively. For bimodal traffic, these improvements are 20 and 21% respectively. Additionally, the bypass utilization is largely independent of the number of VCs when using shared buffers and very competitive with few private ones, allowing to simplify the allocation mechanisms.

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Section: Introductionmentioning

confidence: 88%

Efficient bypass in mesh and torus NoCs

Perez

Vallejo

Beivide

2020

Journal of Systems Architecture

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“…Since the buffers in NoCs are more precious than in off-chip networks due to the tight area and power budgets, this mechanism ensures that a reserved but nonempty VC can be re-allocated to another packet. In [22], the authors also propose a mechanism that allows to bypass flits even if the buffers to bypass are not empty. It can be applied to wormhole and virtual cut-through to reduce packet latency and power consumption.…”

Section: Flow Control In Nocsmentioning

confidence: 99%

Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

Wang

2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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We propose a Network-on-Chip (NoC)-based whole system design, whose communication architecture is compatible with the AMBA AXI4 protocol and supports high-performance multiple Quality-of-Service (QoS) schemes. In our system, the network interface (NI) between the NoC and the master/slave node is proposed to make the NoC architecture independent from the AXI4 protocol via message format conversion between the AXI4 signal format and the packet format, offering high flexibility to the NoC design. Besides, a QoS inheritance mechanism is applied in the slave-side NI to support QoS during packets' round-trip transfer in the NoC. The NoC system contains Time Division Multiplexing (TDM) and Virtual Channel (VC) subnetworks to apply multiple QoS schemes to AXI4 signals with different QoS tags and the NI is responsible for signals distribution between two subnetworks. Besides, a traffic converter is proposed in each NI to balance the traffic between the two subnetworks when necessary. The experimental results show that our proposed architecture ensures a high-throughput and lowlatency NoC system. By applying traffic converter, the packet latency can be improved.

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“…However, it has little impact on those communications between neighboring nodes and the bypass is completed only when enough buffer resource is available. To maximize the utilization of the bypass, Non-Empty Buffer Bypass (NEBB) is proposed [18]. As its name implies, the NEBB NoC allows bypassing a non-empty buffer for single-flit packets or multi-flit packets that there are enough buffers in its destination node.…”

Section: Related Workmentioning

confidence: 99%

“…For these low-radix networks, reducing the latency of each router is an alternative approach. With aggressive lookahead routing, speculative stages and router bypass mechanisms, transmission delay in such a system has been reduced by optimizing router micro-architecture [14][15][16][17][18][19][20][21][22][23]. Among these approaches, single-cycle multi-hop asynchronous repeated traversal (SMART) network that skips several intermediate routers within a single cycle, achieves a better performance with acceptable area cost [19][20][21][22][23].…”

Section: Introductionmentioning

confidence: 99%

A Latency-Optimized Network-on-Chip with Rapid Bypass Channels

Ma¹,

Gao²,

Gao³

et al. 2021

Micromachines

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Network-on-Chips with simple topologies are widely used due to their scalability and high bandwidth. The transmission latency increases greatly with the number of on-chip nodes. A NoC, called single-cycle multi-hop asynchronous repeated traversal (SMART), is proposed to solve the problem by bypassing intermediate routers. However, the bypass setup request of SMART requires additional pipeline stages and wires. In this paper, we present a NoC with rapid bypass channels that integrates the bypass information into each flit. In the proposed NoC, all the bypass requests are delivered along with flits at the same time reducing the transmission latency. Besides, the bypass request is unicasted in our design instead of broadcasting in SMART leading to a great reduction in wire overhead. We evaluate the NoC in four synthetic traffic patterns. The result shows that the latency of our proposed NoC is 63.54% less than the 1-cycle NoC. Compared to SMART, more than 80% wire overhead and 27% latency are reduced.

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Efficient Router Bypass via Hybrid Flow Control

Cited by 10 publications

References 12 publications

Efficient bypass in mesh and torus NoCs

Efficient bypass in mesh and torus NoCs

Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

A Latency-Optimized Network-on-Chip with Rapid Bypass Channels

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