Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET

Dhanuskodi, Siva Nishok; Allen, Samuel; Holcomb, Daniel

doi:10.1109/tvlsi.2020.2999593

Cited by 9 publications

(3 citation statements)

References 36 publications

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“…Yu et al [26], in 2019, synthesized the most effective characteristics from previous designs, resulting in a design with a GE of 1960 while still achieving a satisfactory execution time of 216 cycles. In 2020, Dhanuskodi et al [9] proposed a methodology that effectively reduced state register activity to a single update per round. This approach resulted in an area with a GE of 886 and 160 cycles, thereby effectively optimizing resource utilization while maintaining a satisfactory performance.…”

Section: Related Workmentioning

confidence: 99%

“…Several lightweight AES implementations have been proposed with the objective of minimizing both the area and power consumption. The objective of these accelerators is to enhance the efficiency of the conventional 128-bit data path by reducing it to 8 bits, as demonstrated in various research studies, such as Lu et al [8], Dhanuskodi et al [9], Wamser and Sauer [10], and Banik et al [11]. The aforementioned reduction leads to a decrease in the number of SBOXes from 16 to 1, thereby resulting in a more condensed hardware design and reduced power consumption.…”

Section: Introductionmentioning

confidence: 99%

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The Security Evaluation of an Efficient Lightweight AES Accelerator

Aljuffri,

Huang,

Muntenaar

et al. 2024

Cryptography

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The Advanced Encryption Standard (AES) is widely recognized as a robust cryptographic algorithm utilized to protect data integrity and confidentiality. When it comes to lightweight implementations of the algorithm, the literature mainly emphasizes area and power optimization, often overlooking considerations related to performance and security. This paper evaluates two of our previously proposed lightweight AES implementations using both profiled and non-profiled attacks. One is an unprotected implementation, and the other one is a protected version using Domain-Oriented Masking (DOM). The findings of this study indicate that the inclusion of DOM in the design enhances its resistance to attacks at the cost of doubling the area.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

The Security Evaluation of an Efficient Lightweight AES Accelerator

Aljuffri,

Huang,

Muntenaar

et al. 2024

Cryptography

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show abstract

“…The Internet of Things (IoT) paves another way for the AES research. The works, [37]- [40], proposed lightweight or area-efficient AES cryptographic circuits. In [41], lightweight AES, PRESENT, and GIFT ciphers were evaluated on FPGA.…”

Section: Introductionmentioning

confidence: 99%

VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

et al. 2022

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This work aims at optimizing the hardware implementation of the SubBytes and inverse SubBytes operations in the advanced encryption standard (AES). To this, the composite field arithmetic (CFA) is employed to optimize all building blocks in S-box (and inverse S-box) of SubBytes (and inverse SubBytes) transformation. A joint design of S-box and inverse S-box is also proposed to further enhance the area efficiency. Specifically, the area of multiplier in the Galois composite field, GF((2 2 ) 2 ), is reduced. The squaring and multiplication with constant λ in GF((2 2 ) 2 ) are combined and optimized as well. Moreover, the multiplicative inversion in GF((2 2 ) 2 ) is manually optimized. Furthermore, the S-box and inverse Sbox are combined and optimized using the pre_processing and post_processing modules. To increase the throughput, a balanced and pipelined architecture is derived. Using the proposed architecture, a throughput of 5.79 Gbps for the S-box can be achieved on Virtex-6 XC6VLX240T and 10% better than the conventional work. According to the ASIC implementation result, the proposed design can still achieve the highest area efficiency and approximately 30% better than conventional works using TSMC 90nm process.INDEX TERMS Advanced encryption standard (AES), Composite field arithmetic (CFA), S-box, VLSI architecture.

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Novel Experimental Prototype for Determining Malicious Degree in Vulnerable Environment of Internet-of-Things

Anil

2022

Cybernetics Perspectives in Systems

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Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET

Cited by 9 publications

References 36 publications

The Security Evaluation of an Efficient Lightweight AES Accelerator

The Security Evaluation of an Efficient Lightweight AES Accelerator

VLSI Architecture of S-Box With High Area Efficiency Based on Composite Field Arithmetic

Novel Experimental Prototype for Determining Malicious Degree in Vulnerable Environment of Internet-of-Things

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