Efficient reconfigurable embedded parsers

TELIOS: A Tool for the Automatic Generation of Logic Programming Machines

“…Chiang & Fu [3] parallelized Early's parsing algorithm [7], introducing a new operator ⊗ and proposed a new architecture which requires n * (n+1) 2 processing elements (PEs) for computing the parse table. A new combination circuit was proposed in [11] for the implementation of the ⊗ operator. In this paper a modification of the parsing algorithm of [11] has been done in order to compute the elements of the parse table PT by the use of only n processing elements that each one handled the cells belonging to the same column of the PT.…”

“…A new combination circuit was proposed in [11] for the implementation of the ⊗ operator. In this paper a modification of the parsing algorithm of [11] has been done in order to compute the elements of the parse table PT by the use of only n processing elements that each one handled the cells belonging to the same column of the PT.…”

“…The effort of designing hardware capable of supporting the declarative programming model, for logic derivations, can now lead to intelligent embedded designs which are considerably more efficient compared to the traditional ones. Some efforts have been done in the past, towards this direction [4], [11], [6] . In [4] a hardware parser was presented based on the CYK parsing algorithm.…”

“…In [4] a hardware parser was presented based on the CYK parsing algorithm. In [11] another hardware parser was presented based on the Earley's parallel algorithm [7]. Both parsers have been implemented using FPGAs.…”

“…The modification of the hardware parser of [11], in order to be used for logic programming applications. It is noted that the parser of [11] is two orders of magnitude faster than the one used in [6]. 2.…”