Efficient reconfigurable architectures of generic cyclic convolution

Krill, B.; Amira, Abbes

doi:10.1109/isce.2011.5973893

Cited by 4 publications

(5 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…There are proposals targeting reconfigurable individual communication function blocks, such as reconfigurable convolutional encoder [18], reconfigurable interleaver [19,20], and reconfigurable IQ mapper [21], etc. These manually designed reconfigurable function blocks achieve high performance when implemented in ASIC while having similar programmability to FPGAs and processors.…”

Section: Related Workmentioning

confidence: 99%

“…After that the reconfigurable pipelined coprocessor was designed to support 802.11a, 802.11b and UWB. Note that all data rates in these protocols are supported, including data rates of 6,9,12,18,24,36, 48 and 54Mbps (indicated as 11a R0 upto 11a R7) for 802.11a, 1, 2, 5.5 and 11Mbps (depicted as 11b R0 to 11b R3) for 802.11b, 53.3, 80, 106.7, 160, 200, 320, 400 and 480Mbps (UWB R0 to UWB R7) for UWB.…”

Section: Programming Of the Coprocessor And Mode Switchingmentioning

confidence: 99%

See 1 more Smart Citation

Reconfigurable pipelined coprocessor for multi-mode communication transmission

Tang

Ambrose

Parameswaran

2013

Proceedings of the 50th Annual Design Automation Conference

View full text Add to dashboard Cite

The need to integrate multiple wireless communication protocols into a single low-cost, low-power hardware platform is prompted by the increasing number of emerging communication protocols and applications. This paper presents a novel application specific platform for integrating multiple wireless communication transmission baseband protocols in a pipelined coprocessor, which can be programmed to support various baseband protocols. This coprocessor can dynamically select the suitable pipeline stages for each baseband protocol. Moreover, each carefully designed stage is able to perform a certain signal processing function in a reconfigurable fashion. The proposed platform is flexible (compared to ASICs) and is suitable for mobile applications (compared to FPGAs and processors). The area footprint of the coprocessor is smaller than an ASIC or FPGA implementation of multiple individual protocols, while the overhead of throughput is 34% worse than ASICs and 32% better than FPGAs. The power consumption is 2.7X worse than ASICs but 40X better than FPGAs on average. The proposed platform outperforms processor implementation in all area, throughput and power consumption. Moreover, fast protocol switching is supported. Wireless LAN (WLAN) 802.11a, WLAN 802.11b and Ultra Wide Band (UWB) transmission circuits are developed and mapped to the pipelined coprocessor to prove the efficacy of our proposal.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Programming Of the Coprocessor And Mode Switchingmentioning

confidence: 99%

Reconfigurable pipelined coprocessor for multi-mode communication transmission

Tang

Ambrose

Parameswaran

2013

Proceedings of the 50th Annual Design Automation Conference

View full text Add to dashboard Cite

show abstract

“…Hartung [18] presents accelerated implementation of spatially-varying kernel image convolution in multi-cores with GPUs. In [19], two different generic cyclic convolution architectures have been synthesized and implemented on DSP blocks, achieving a raw calculation rate of 27.8 frames per second (fps) with a resolution of 600 × 600 pixels. However, the transform length order of the processor [19] is fixed, thus constraining its use to specific applications.…”

Section: Introductionmentioning

confidence: 99%

“…In [19], two different generic cyclic convolution architectures have been synthesized and implemented on DSP blocks, achieving a raw calculation rate of 27.8 frames per second (fps) with a resolution of 600 × 600 pixels. However, the transform length order of the processor [19] is fixed, thus constraining its use to specific applications. Mohammad [20] proves the feasibility of ASIC that performs a convolution on an acquired image.…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, the long execution time caused by the enormous number of calculation is unacceptable and is a serious problem that should be solved [24][25][26]. Many approaches using hardware and software have been implemented to reduce convolution processing time [16,19,20,25,27]. The limiting conditions in the implementation of convolution are area, speed, and hardware occupation.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Hardware Implementation of Reconfigurable 1D Convolution

Rao

Bin

Zhao

2015

J Sign Process Syst

View full text Add to dashboard Cite

Convolution has been extensively used in image processing and computer vision, including image enhancement, smoothing, and structure extraction. However, convolution operation typically requires a significant amount of computing resources. A novel one-dimensional (1D) convolution processor with reconfigurable architecture is implemented in this study. This processor is a combination of a line buffer, controller units, as well as a reconfigurable and separable convolution module. The use of a reconfigurable architecture and separable convolution approach improves the flexibility and performance of the convolution processor. The reconfigurable and separable convolution array, which is the main component of the processor, can simultaneously execute convolution operation with different kernels, with a maximum kernel size of up to 24 × 24. Experimental results show that the maximum frames rate of the processor is approximately 194 frames per second (fps), which exceeds the real-time requirement. Synthesis results show that the processor occupies 13.39 mm 2 at a 204 MHz system clock and consumes a power of 419 mW at maximum kernel size at a 120 MHz system clock in SMIC 0.18 μm CMOS technology. Verification experiments on field programmable gate arrays (FPGAs) demonstrate that the processor is suitable for realtime image processing applications even for high-resolution images.

show abstract