Efficient realisation of MOS-NDR threshold logic gates

Abstract

A novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms of area and power consumption, has been performed to demonstrate that the proposed circuit is more efficient than a similar reported structure. Introduction: Negative differential resistance (NDR) devices can be used in the design of logic circuits owing to their unique NDR current -voltage (I -V) characteristic. This property can be exploited to significantly increase the functionality implemented by a single gate (in comparison to CMOS and bipolar technologies) [1]. Recently, resonant tunnelling diodes (RTD) have been widely used to demonstrate the operation of logic circuits that take advantage of the properties of NDR devices. In particular, a number of threshold gates (TGs) based on RTDs monolithically integrated with three-terminal devices, which implement complex logic functions, have been fabricated and have demonstrated high speed and robust operation [2]. Reciprocally, circuit ideas coming from RTD-based designs can be extended to an 'all CMOS' environment consisting of MOS-NDR devices [3 -5].In this Letter, we propose a new programmable MOS-NDR device that can be used to obtain efficient realisations of threshold logic gates, as occurs with RTDs. To prove this, we have selected a key circuit the performance of which, in terms of area and power consumption, can be improved with regard to other MOS-NDR or CMOS realisations.

Multiple negative differential resistance devices with ultra-high peak-to-valley current ratio for practical multi-valued logic and memory applications

“…3(a). 22,23) Figure 3(b) shows the various voltage transfer curves (VTCs: V G -V IN ) of the inverter according to the threshold voltage of mn1 and mp1 (V th,mn1 and V th,mp1 ). When the V th,mn1 is increased from 0.15 to 0.88 V, the transition voltage (V M ) is increased from 0.5 V (black-solid line) to 0.9 V (red-dashed line) in companied with faster switching characteristic owing to transition at the subthreshold region, which lead to high second PVCR and NDR gain.…”

Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs

“…The first and the third follower are falling edge-triggered, whereas the second one is rising edge-triggered. They have been implemented with MOS-NDR devices (circuit made up of transistors that emulate the RTD I-V characteristic) and the MOBILE gate topology from [14] in a 1.2V-130nm CMOS commercial technology. analyzer Agilent 16902B.…”

Programmable negative differential resistance device using FED

“…Hence, a CMOS-compatible version of NDR is desirable. The Λ-type circuit configuration is commonly used to reach the MOS-NDR devices that are composed of several MOSFETs [3,4].…”