Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment

Kumar, Rakesh; Martínez, Alejandro Rosillo; González, Antonio

doi:10.1145/2629681

Cited by 11 publications

(4 citation statements)

References 25 publications

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“…Abdel-Majeed et al enlarges the idle period of functional units in a GPU through dynamic instruction issue policies [29]. Kumar et al proposed algorithms to power off parts of vector lanes in an SIMD accelerator [30]. Aghilinasab et al proposed algorithms to power off vector functional units in a GPU [31].…”

Section: B Related Work: Compiler-directed Leakage Power Controlmentioning

confidence: 99%

Compiler-Directed Parallelism Scaling Framework for Performance Constrained Energy Optimization

2020

IEEE Access

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Evolution of semiconductor manufacturing technology leads to the rising trend of leakage current and the end of Dennard scaling. At the dark silicon era, aggressive power gating scheme with quantitative management on power-gated hardware resources is required. This paper proposes a novel approach-parallelism scaling-to control static energy on power-gated parallel hardware. This work presents performance-constrained optimization method to power off the greatest possible amount of hardware. As a first trial, this paper examines the idea on VLIW-style architecture exploiting instruction-level parallelism. This paper establishes a theoretical foundation to realize parallelism scaling. The mathematical programming theory includes (1) topological model to control the granularity of program partitioning, (2) optimal partitioning on well-structured control flow graph in polynomial time, and (3) decision support for parallelism through item packing model guided by energy density. Evaluation conducted on EEMBC Denbench benchmark suite shows at least 15% to 53% saving on static energy compared to non-powergated architecture. Compared to the state-of-art resource management scheme, our approach saves about 20% to 30% energy to meet the same performance demand. The evaluation reveals noteworthy opportunity to save static energy for future dark-silicon architecture design.

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Section: B Related Work: Compiler-directed Leakage Power Controlmentioning

confidence: 99%

Compiler-Directed Parallelism Scaling Framework for Performance Constrained Energy Optimization

2020

IEEE Access

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“…Kumar et al [21] use such an approach to improve the efficiency of power-gating the processor's SIMD unit. In this scenario, devectorizing parts of the program reduces the speedup caused by SIMD instructions, but reduces the power-gating overhead.…”

Section: Profile-guided Software Modificationsmentioning

confidence: 99%

Dim Silicon and the Case for Improved DVFS Policies

Gottschlag,

Khalil,

Bellosa

2020

Preprint

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Due to thermal and power supply limits, modern Intel CPUs reduce their frequency when AVX2 and AVX-512 instructions are executed. As the CPUs wait for 670 µs before increasing the frequency again, the performance of some heterogeneous workloads is reduced. In this paper, we describe parallels between this situation and dynamic power management as well as between the policy implemented by these CPUs and fixed-timeout device shutdown policies. We show that the policy implemented by Intel CPUs is not optimal and describe potential better policies. In particular, we present a mechanism to classify applications based on their likeliness to cause frequency reduction. Our approach takes either the resulting classification information or information provided by the application and generates hints for the DVFS policy. We show that faster frequency changes based on these hints are able to improve performance for a web server using the OpenSSL library.

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“…In these works, dynamic configurability enables lane resource to execute as a traditional SIMD processor, be re-purposed to behave as a clustered VLIW processor, or combinations of both. On the other hand, the work presented in [17] uses power gating for turning off the lanes of the SIMD function units in the case of low DLP and the corresponding portion of the code is devectorized to keep the higher lanes off. The devectorized code is executed on the lowest SIMD lane.…”

Section: Related Workmentioning

confidence: 99%

Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths

Diken

O’Riordan²,

Jordans

et al. 2015

2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

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Abstract-The degree of DLP parallelism in applications is not fixed and varies due to different computational characteristics of applications. On the contrary, most of the processors today include single-width SIMD (vector) hardware to exploit DLP. However, single-width SIMD architectures may not be optimal to serve applications with varying DLP and they may cause performance and energy inefficiency. We propose the usage of VLIW processors with multiple native vector-widths to better serve applications with changing DLP. SHAVE is an example of such VLIW processor and provides hardware support for the native 32-bit and 128-bit wide vector operations. This paper researches and implements the mixed-length SIMD code generation support for SHAVE processor. More specifically, we target generating 32-bit and 128/64-bit SIMD code for the native 32-bit and 128-bit wide vector units of SHAVE processor. In this way, we improved the performance of compiler generated SIMD code by reducing the number of overhead operations and by increasing the SIMD hardware utilization. Experimental results demonstrated that our methodology implemented in the compiler improves the performance of synthetic benchmarks up to 47%.

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Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment

Cited by 11 publications

References 25 publications

Compiler-Directed Parallelism Scaling Framework for Performance Constrained Energy Optimization

Compiler-Directed Parallelism Scaling Framework for Performance Constrained Energy Optimization

Dim Silicon and the Case for Improved DVFS Policies

Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths

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