Efficient Power Conservation using adiabatic subtracter

Abstract

Adiabatic logic is commonly used to reduce the energy loss during the charging and discharging process of circuit operation. Adiabatic logic is also known as "energy recovery" or "charge recovery" logic. The adiabatic logic uses AC power supply instead of constant DC supply.This is one of the main reasons in the reduction of power dissipation. This paper describes implementation full subtractor. The simulation results of CMOS design are compared with different adiabatic logic styles such as efficient charge recovery logic (ECRL) and positive feedback adiabatic logic (PFAL).The simulation results indicate that the proposed technique is advantageous in many of the low power digital applications. The design is implemented using Tanner tool.