Efficient Overlay Architecture Based on DSP Blocks

Throughput Oriented FPGA Overlays Using DSP Blocks

“…Previous work has demonstrated that the DSPrich FPGA fabrics in modern devices can support general purpose processing at near to DSP block theoretical limits [13], [14]. This has resulted in the development of overlays with improved frequency and throughput [8], [12], however, these overlays still suffer from significant resource overheads, specifically in the routing network. While techniques such as runtime LUT content manipulation [15] and interconnect multiplexing [16] can reduce routing network overheads, they become unsuitable as the overlay frequency approaches the theoretical limit of the FPGA fabric.…”

“…As FPGAs have increased in size, these benchmarks are no longer sufficient to fully test newer more efficient overlays. We have compiled a benchmark set (shown in Table I) containing a number of compute kernels from the literature [12], [18], [19], [20]. Table I shows the characteristics of the kernels after extracting the data flow graphs (DFGs), including the number of I/O nodes, graph edges, operation nodes, average parallelism, graph depth, and graph width.…”

“…Using fully pipelined DSP blocks as the functional units allows us to achieve very high throughput. To improve the compute to routing ratio and hence reduce the number of slices per DSP block in the implementation of the overlay, we improve the FU in [12] by using two DSP48E1 blocks. The FU, shown in Fig.…”

“…2. It can be seen that the 4N-4D architecture is only suitable for a very small number of [5] sgfilter [10] mibench [6] qspline [22] poly1 [6] poly2 [6] poly3 [7] poly4 [3] poly5 [14] poly6[25] poly7 [21] poly8 [17] fft [8] kmeans [20] mm [8] mri [7] spmv [8] stencil [8] conv [8] radar [6] arf [20] fir2 [8] hornerbezier [8] motionvector [12] 12N 8N 4N kernels (those below the 4N-4D curve), with a significant underutilization of DSP blocks for the other kernels, and is not considered further. Similarly, the scalability curves for the 8N architecture with an FU consisting of one, two, and four DSP blocks was also considered, referred to as 8N-1D, 8N-2D and 8N-4D in Fig.…”

“…An overlay architecture with FUs based on Xilinx DSP blocks was proposed in [12]. The overlay combines multiple kernel operations in a single tile mapped to DSP blocks resulting in a significant reduction in the number of FUs required, and hence the routing overhead.…”