Efficient output ESD protection for 0.5-μm high-speed CMOS SRAM IC with well-coupled technique

Ker, Ming‐Dou; Wu, Chau-Neng

doi:10.1016/0026-2714(96)00185-0

Microelectronics Reliability

1996

DOI: 10.1016/0026-2714(96)00185-0

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Efficient output ESD protection for 0.5-μm high-speed CMOS SRAM IC with well-coupled technique

Ming‐Dou Ker

Chau-Neng Wu

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Efficient output ESD protection for 0.5-μm high-speed CMOS SRAM IC with well-coupled technique

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