Efficient One-Step Decodable Limited Magnitude Error Correcting Codes for Multilevel Cell Main Memories

Das, Abhishek; Touba, N.A.

doi:10.1109/tnano.2019.2917139

Cited by 7 publications

(2 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The code in [37] is an enhanced version of OLS codes which is based on H matrix. Similarly, in [38] and [39], the enhanced versions of OLS code are proposed which consider limited magnitude. Each method reduces a code length by considering the limited magnitude at cost of a slight increase in decoding and encoding latency.…”

Section: Related Workmentioning

confidence: 99%

Cost-Effective Reliable MLC PCM Architecture Using Virtual Data Based Error Correction

2020

View full text Add to dashboard Cite

The existing charge-based memories like DRAM and flash are reaching their scaling limits. Phase change memory (PCM) is one of the most promising emerging memory technologies due to its good scalability and low leakage power. Multi-level cell (MLC) operation in PCM, which stores two or more bits in a single cell, is necessary to achieve a high storage density. However, a reduced resistance range in multiple storage levels of MLC PCM, introduces a lot of soft errors because of the resistance drift phenomenon. The poor reliability of MLC PCM requires strong error correction codes (ECC) which could severely degrade the storage density and performance. In this paper, we propose a cost-effective reliable MLC PCM architecture for improving MLC PCM reliability, storage density and performance. The proposed architecture exploits the data-dependent nature of resistance drift problem to reduce the ECC overhead. A simple state mapping is used to generate virtual data, which is half of the actual data size. ECC parity bits are generated based on virtual data bits instead of actual message bits, thus resulting in a reduced number of cells for parity bits. This improves the reliability and storage density of MLC PCM. The performance is also improved by minimizing the ECC overhead. Simulation results show an improvement of about 10 4 times in reliability and 10.9% in storage density compared to a conventional MLC PCM which uses a typical error correction scheme. Performance and energy efficiency are also improved up to 13.7% and 10%, respectively, by the proposed architecture. INDEX TERMS Emerging memories, phase change memory (PCM), MLC PCM, resistance drift, error correction code (ECC).

show abstract

Section: Related Workmentioning

confidence: 99%

Cost-Effective Reliable MLC PCM Architecture Using Virtual Data Based Error Correction

2020

View full text Add to dashboard Cite

show abstract

“…HE protection of storage systems such as memories against soft errors (caused by phenomena such as Single Event Upsets (SEUs)) has been widely studied in the technical literature; these errors can lead to data corruption and in some cases even to a system failure [1]- [4]. Error detection and correction codes (EDCCs) initially applicable to errors in data transmission are also commonly used to protect memories (including both conventional CMOS memories [5], [6] and emerging next-generation memories based on alternative technologies [7], [8]) in the presence of soft errors. Different from protecting data in communication channels, EDCCs with a smaller number of parity bits and a lower complexity for decoding are better suitable to memory application.…”

Section: Introductionmentioning

confidence: 99%

Protection of Associative Memories Using Combined Tag and Data Parity (CTDP)

Liu

Reviriego

Lombardi

2021

IEEE Trans. Nanotechnology

View full text Add to dashboard Cite

As emerging memories are utilized in processors as main memory, they must also coexist with CMOS memories; for instance SRAMs, are used to implement smaller, but faster associative memories. These hybrid designs exploit the advantages of both types of memories to achieve better performance. For some applications, the improvement in performance for on-chip associative memories is crucial for the overall computing system. For CMOS memories, soft errors are a major concern because they flip bits and can lead to data corruption and even a system failure. Error Detection and Correction Codes (EDCCs) are commonly used to protect memories against soft errors. In associative memories, an entry is formed by a tag and its associated data (or value). EDCCs are typically used to separately protect the tag and the data. This paper considers the protection of associative memories in which false negatives do not cause a failure. A Combined Tag and Data Parity (CTDP) protection scheme is proposed. This new approach utilizes a single parity bit per entry, so it reduces the number of parity bits needed to protect an entry as well as the memory size. The proposed scheme also reduces the complexity of read operations; it incurs the lowest circuit overhead for the protection circuitry in terms of area, delay and power consumption when compared to other schemes found in the technical literature. This makes the proposed scheme germane to associative memories used in hybrid designs that combine SRAMs and emerging memories. The extension of the proposed scheme to stronger codes is also discussed.

show abstract

Trade-off Mechanism Between Reliability and Performance for Data-flow Soft Error Detection

Zhao,

Chen,

2023

J Electron Test

View full text Add to dashboard Cite

Efficient One-Step Decodable Limited Magnitude Error Correcting Codes for Multilevel Cell Main Memories

Cited by 7 publications

References 11 publications

Cost-Effective Reliable MLC PCM Architecture Using Virtual Data Based Error Correction

Cost-Effective Reliable MLC PCM Architecture Using Virtual Data Based Error Correction

Protection of Associative Memories Using Combined Tag and Data Parity (CTDP)

Trade-off Mechanism Between Reliability and Performance for Data-flow Soft Error Detection

Contact Info

Product

Resources

About