Efficient Multitasking on FPGA Using HDL-Based Checkpointing

Vu, Hoang-Gia; Nakada, Takashi; Nakashima, Yasuhiko

doi:10.1007/978-3-319-78890-6_47

Cited by 4 publications

(1 citation statement)

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“…As an important remark, note that the above low-level mechanism can enable a full range of scenarios in addition to preemption. It can also be useful for supporting process migration across different implementations, as an underlying mechanism for reliability, or for checkpointing of long or critical FPGA tasks [15]. We thus plan to fully integrate the flow with the software layers in the MPSoC and make the low-level mechanisms accessible to, and controlled by the operating system/hypervisor.…”

Section: Fpga Managementmentioning

confidence: 99%

SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms

et al. 2021

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This paper presents SPHERE, a project aimed at the realization of an integrated framework to abstract the hardware complexity of interconnected, modern system-on-chips (SoC) and simplify the management of their heterogeneous computational resources. The SPHERE framework leverages hypervisor technology to virtualize computational resources and isolate the behavior of different subsystems running on the same platform, while providing safety, security, and real-time communication mechanisms. The main challenges addressed by SPHERE are discussed in the paper along with a set of new technologies developed in the context of the project. They include isolation mechanisms for mixed-criticality applications, predictable I/O virtualization, the management of time-sensitive networks with heterogeneous traffic flows, and the management of field-programmable gate arrays (FPGA) to provide efficient implementations for cryptography modules, as well as hardware acceleration for deep neural networks. The SPHERE architecture is validated through an autonomous driving use-case.INDEX TERMS cyber-physical systems, embedded systems, real-time systems, hypervisor, FPGA.

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Section: Fpga Managementmentioning

confidence: 99%