Efficient Microprocessor Verification using Antecedent Conditioned Slicing

Vasudevan, Shobha; Viswanath, Vinod; Abraham, Jacob A.

doi:10.1109/vlsid.2007.70

Cited by 3 publications

(1 citation statement)

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“…It was first introduced by Weiser [7] and is used in fields such as software debugging, maintenance and testing. In RTL verification space, it has mainly been applied to formal verification space [8,9]. For a specified variable in a given HDL description, a slice is a subset of the original design that produces same behavioral for the variable (known as slice target variable or STV).…”

Section: B Optimized Design Slicesmentioning

confidence: 99%

Efficient Online RTL Debugging Methodology for Logic Emulation Systems

Banerjee¹,

Gupta²

2012

2012 25th International Conference on VLSI Design

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The offline debugging model provided by logic emulation systems has some specific disadvantages. Since analysis of signal traces and bug fixing is decoupled from emulation run, validation of a potential fix requires a costly iteration through design recompilation and mapping process, followed by fresh emulation run. This slows down overall verification process. This paper presents an online debugging methodology to achieve rapid verification closure with capability to execute the design back and forward for debug. On encountering an error, the design under test (DUT) can be reverse executed step-by-step to locate source of the error. A two pass emulation technique is used to generate checkpoints and traces needed to support reverse execution. Easy and efficient reverse execution based debug is supported using an innovative technique called optimized design slicing, which allows debug along a meaningful design portion likely to cause the error being investigated. Once the source of error is located, potential bug fixes can be evaluated online by forcing a set of signals to desired values, without going through the design recompilation process and restarting emulation from time 0. Benchmarks on several customer designs have shown that the methodology enhances verification performance significantly.

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Section: B Optimized Design Slicesmentioning

confidence: 99%