Efficient memory virtualization for Cross-ISA system mode emulation

Chang, Chao-Jui; Wu, Jan‐Jan; Hsu, Wei-Chung; Liu, Pangfeng; Yew, Pen-Chung

doi:10.1145/2576195.2576201

Cited by 16 publications

(7 citation statements)

References 7 publications

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“…However this flexibility comes at a significant cost in performance, in particular due to the need to handle virtual memory address translation within the guest. This requires either translating guest page tables to the host page table format [12] or performing guest page table walks in software and caching the results in a software TLB [37].…”

Section: Proposed Approachmentioning

confidence: 99%

HyperMAMBO-X64

d'Antras¹,

Gorgovan²,

Garside³

et al. 2017

Proceedings of the 13th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments

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Current computer architectures-ARM, MIPS, PowerPC, SPARC, x86-have evolved from a 32-bit architecture to a 64-bit one. Computer architects often consider whether it could be possible to eliminate hardware support for a subset of the instruction set as to reduce hardware complexity, which could improve performance, reduce power usage and accelerate processor development. This paper considers the scenario where we want to eliminate 32-bit hardware support from the ARMv8 architecture. Dynamic binary translation can be used for this purpose and generally comes in one of two forms: application-level translators that translate a single user mode process on top of a native operating system, and system-level translators that translate an entire operating system and all its processes. Application-level translators can have good performance but is not totally transparent; system-level translators may be 100% compatible but performance suffers. HyperMAMBO-X64 uses a new approach that gets the best of both worlds, being able to run the translator as an application under the hypervisor but still react to the behavior of guest operating systems. It works with complete transparency with regards to the virtualized system whilst delivering performance close to that provided by hardware execution. A key factor in the low overhead of HyperMAMBO-X64 is its deep integration with the virtualization and memory management features of ARMv8. These are exploited to support caching of translations across multiple address spaces while ensuring that translated code remains consistent with the source instructions it is based on. We show how these attributes are achieved without sacrificing either performance or accuracy.

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Section: Proposed Approachmentioning

confidence: 99%

HyperMAMBO-X64

d'Antras¹,

Gorgovan²,

Garside³

et al. 2017

Proceedings of the 13th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments

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“…It has been well established [Magnusson and Werner 1994;Chang et al 2014;Wang et al 2015;Hong et al 2015] that emulation of a guest MMU is one of the most time-consuming parts of cross-architecture virtualization; therefore, in this motivating example, we will focus on the memory address translation process required for virtualization. For this, consider the diagram in Figure 1, which shows the percentage…”

Section: Motivating Examplementioning

confidence: 99%

“…As described in the motivating example (Section 1.1), the MMUs between two different architectures behave quite differently, and traditional full-system cross-architecture virtualization uses a (correct but slow) software MMU implementation to emulate this subsystem. Thus, much work has been done [Wang et al 2015;Chang et al 2014;Hong et al 2015] in the area of software MMUs to reduce the translation penalty and hence increase overall throughput of the virtualization system.…”

Section: Mmu Virtualizationmentioning

confidence: 99%

“…Early work in the context of Simics introduced a software caching mechanism that improved the performance of interpreted memory operations by reducing the number of calls to complex memory simulation code [Magnusson and Werner 1994]. More recently, Chang et al [2014], Wang et al [2015], and Hong et al [2015] have presented novel schemes for speeding up address translation in full-system simulators. These two schemes are the closest matches to our work documented in the literature.…”

Section: Related Workmentioning

confidence: 99%

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Hardware-Accelerated Cross-Architecture Full-System Virtualization

Spink

Wagstaff

Franke

2016

ACM Trans. Archit. Code Optim.

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Hardware virtualization solutions provide users with benefits ranging from application isolation through server consolidation to improved disaster recovery and faster server provisioning. While hardware assistance for virtualization is supported by all major processor architectures, including Intel, ARM, PowerPC, and MIPS, these extensions are targeted at virtualization of the same architecture, for example, an x86 guest on an x86 host system. Existing techniques for cross-architecture virtualization, for example, an ARM guest on an x86 host, still incur a substantial overhead for CPU, memory, and I/O virtualization due to the necessity for software emulation of these mismatched system components. In this article, we present a new hardwareaccelerated hypervisor called CAPTIVE, employing a range of novel techniques that exploit existing hardware virtualization extensions for improving the performance of full-system cross-platform virtualization. We illustrate how (1) guest memory management unit (MMU) events and operations can be mapped onto host memory virtualization extensions, eliminating the need for costly software MMU emulation, (2) a block-based dynamic binary translation engine inside the virtual machine can improve CPU virtualization performance, (3) memory-mapped guest I/O can be efficiently translated to fast I/O specific calls to emulated devices, and (4) the cost for asynchronous guest interrupts can be reduced. For an ARM-based Linux guest system running on an x86 host with Intel VT support, we demonstrate application performance levels, based on SPEC CPU2006 benchmarks, of up to 5.88× over state-of-the-art QEMU and 2.5× on average, achieving a guest dynamic instruction throughput of up to 1280 MIPS (million instructions per second) and 915.52 MIPS, on average.

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“…However, even with SoftTLB, memory translation still consumes a significant portion of execution time. For example, Chang et al [2014] reported that QEMU spends nearly 40% of execution time in memory translation.…”

Section: Introductionmentioning

confidence: 99%

Optimizing Control Transfer and Memory Virtualization in Full System Emulators

Hong

Hsu

Chou

et al. 2015

ACM Trans. Archit. Code Optim.

Self Cite

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Full system emulators provide virtual platforms for several important applications, such as kernel and system software development, co-verification with cycle accurate CPU simulators, or application development for hardware still in development. Full system emulators usually use dynamic binary translation to obtain reasonable performance. This paper focuses on optimizing the performance of full system emulators. First, we optimize performance by enabling classic control transfer optimizations of dynamic binary translation in full system emulation, such as indirect branch target caching and block chaining. Second, we improve the performance of memory virtualization of cross-ISA virtual machines by improving the efficiency of the software translation lookaside buffer (software TLB). We implement our optimizations on QEMU, an industrial-strength full system emulator, along with the Android emulator. Experimental results show that our optimizations achieve an average speedup of 1.98X for ARM-to-X86-64 QEMU running SPEC CINT2006 benchmarks with train inputs. Our optimizations also achieve an average speedup of 1.44X and 1.40X for IA32-to-X86-64 QEMU and AArch64-to-X86-64 QEMU on SPEC CINT2006. We use a set of real applications downloaded from Google Play as benchmarks for the Android emulator. Experimental results show that our optimizations achieve an average speedup of 1.43X for the Android emulator running these applications. CCS Concepts: r General and reference → Metrics; r Software and its engineering → Virtual machines; Runtime environments

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Efficient memory virtualization for Cross-ISA system mode emulation

Cited by 16 publications

References 7 publications

HyperMAMBO-X64

HyperMAMBO-X64

Hardware-Accelerated Cross-Architecture Full-System Virtualization

Optimizing Control Transfer and Memory Virtualization in Full System Emulators

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