Efficient linear feedback shift register design for pseudo exhaustive test generation in BIST

Haridas, Nisha; M, Nirmala Devi

doi:10.1109/icectech.2011.5941621

Cited by 9 publications

(2 citation statements)

References 15 publications

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“…A building block which is used to generate random test pattern is very crucial in BIST construction. Many test pattern generators are employed in BIST, out of those, LFSR is broadly used due to its capability to generate huge random sequences [2].…”

Section: Introductionmentioning

confidence: 99%

Subthreshold Region based Linear Feedback Shift Register

Lakshmi,

Kamaraju,

Babulu

2019

IJEAT

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Growing demand for portable devices and fast increases in complexity of chip cause power dissipation is an important parameter. Power consumption and dissipation or generations of more heat possess a restriction in the direction of the integration of more transistors. Several methods have been proposed to reduce power dissipation from system level to device level. Subthreshold circuits are widely used in more advanced applications due to ultra low-power consumption. The present work targets on construction of linear feedback shift registers (LFSR) in weak inversion region and their performance observed in terms of parameters like power delay product (PDP). In CMOS circuits subthreshold region of operation allows a low-power for ample utilizations but this advantage get with the penalty of flat speed. For the entrenched and high speed applications, improving the speed of subthreshold designs is essential. To enhance this, operate the devices at maximum current over capacitance. LFSR architectures build with various types of D flip flop and XOR gate circuits are analyzed. Circuit level Simulation is carried out using 130 nm technologies.

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Section: Introductionmentioning

confidence: 99%

Subthreshold Region based Linear Feedback Shift Register

Lakshmi,

Kamaraju,

Babulu

2019

IJEAT

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“…Hence, inserting the multiplexers makes the LFSR reconfigurable. [3]select This paper is an n-bit reconfigurable LFSR that generates sequence of maximum length or less has been implemented. This proposed design provides flexibility in both the feedback and size.…”

Section: Introductionmentioning

confidence: 99%

Design and Testing Parallel Prefix Adders using Reconfigurable LFSR in FPGA

Munnur¹

2019

IJRASET

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The main criteria of this paper is to design Reconfigurable Linear Feedback Shift Register (LFSR) for very large scale integration(VLSI) of Integrated Circuit(IC) testing .Comparability to the Automatic Test Equipment(ATE) the Logic Built In Self Test(LBIST) has take into popularity. This logic built which helps in built testing with the help of additional hardware construction indoors the circuit. Thus doesn't contains the test pattern but they generate by the testing circuits. By this can out down the testing cost substantially. LFSR is mostly used as a test pattern generate for IC testing. To improve the fault coverage of IC testing in logic BIST using Reconfigurable LFSR. It is configurable to generate the maximum length of the pattern depending on the feedback polynomial that provide as per requirement. In this paper, the proposed reconfigurable LFSR of four structural represented in modular, standard, hybrid and complete LFSR is simulated in different sizes (8,16,32,64) in Xilinx Spartan 3E with an application of Parallel Prefix Adder (konge stone) of 16-bit.This simulation results shows the increasing of

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