Efficient interconnects for clustered microarchitectures

11th International Symposium on High-Performance Computer Architecture

et al.

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Section: Processor Architecturementioning

confidence: 99%

Distributing the Frontend for Temperature Reduction

Chaparro

Magklis

11th International Symposium on High-Performance Computer Architecture

et al.

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“…These architectures rely on keeping most of the communications local within clusters to achieve high performance. Even if most of the communications are local, inter-cluster communications are required in a non-negligible number of cases (1 communication every 4 instructions may be common in a 4-cluster configuration [13] [14].…”

Section: Related Workmentioning

confidence: 99%

“…Some other mechanisms [4][5][13] [14] have been proposed to deal with the problem of reducing the number of required communications and maximizing workload balance at the same time. These policies are based on using a dependence-based steering algorithm and an additional mechanism to manage workload balance.…”

Section: Related Workmentioning

confidence: 99%

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Inherently Workload-Balanced Clustered Microarchitecture

Abella

19th IEEE International Parallel and Distributed Processing Symposium

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“…Address calculations occur at the execution clusters. Special copy micro-ops communicate register values among the clusters using point-to-point links [16] [22]. GALS systems, by design, assume unrestricted clock skew among domains.…”

Section: Introductionmentioning

confidence: 99%

Using MCD-DVS For Dynamic Thermal Management Performance Improvement

Chaparro

Magklis

Thermal and Thermomechanical Proceedings 10th Intersociety Conference on Phenomena in Electronics Systems, 2006. ITHERM 2006.

et al.

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With chip temperature being a major hurdle in microprocessor design, techniques to recover the performance loss due to thermal emergency mechanisms are crucial in order to sustain performance growth. Many techniques for power reduction in the past and some on thermal management more recently have contributed to alleviate this problem. Probably the most important thermal control technique is dynamic voltage and frequency scaling (DVS) which allows for almost cubic reduction in power with worst-case performance penalty only linear. So far, DVS techniques for temperature control have been studied at the chip level. Finer grain DVS is feasible if a Globally-Asynchronous Locally-Synchronous (GALS) design style is employed. GALS, also known as Multiple-Clock Domain (MCD), allows for an independent voltage and frequency control for each one of the clock domains that are part of the chip. There are several studies on DVS for GALS that aim to improve energy and power efficiency but not temperature. This paper proposes and analyses the usage of DVS at the domain level to control temperature in a clustered MCD microarchitecture with the goal of improving the performance of applications that do not meet the thermal constraints imposed by the designers. KEY WORDS: Multiple clock domain architectures, GALS, DTM, dynamic frequency and voltage scaling INTRODUCTIONPower directly translates into heat which must be removed from the processor die in order to keep the silicon temperature inside a "safe" range. Power density is increasing due to the fact that frequency and leakage current are scaling up so much that their effect on power cannot be offset by decreasing the supply voltage. Such trend makes the cost of the cooling system grow and challenges the performance benefits that can be obtained by the ever growing transistor density. This results in a cooling system cost in the order of $1-$3 or more per Watt when the average power exceeds 40W [1][2], which represents a significant part of the total cost of the chip. This is especially important for data centers where air conditioning is a main contributor in the total cost [3]. In addition, circuit reliability depends exponentially on operating temperature. Temperature variations account for over 50% of electronic failures [4].