Efficient heterogeneous programming with FPGAs using the Controller model

Rodriguez-Canal, Gabriel; Torres, Yuri; Andújar, Francisco J.; González-Escribano, Arturo

doi:10.1007/s11227-021-03792-7

Cited by 8 publications

(6 citation statements)

References 11 publications

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“…Controllers [10] is a heterogeneous programming model implemented as a library that enables performance portability across CPU-cores (using OpenMP), GPUs (using CUDA or OpenCL), Intel FPGAs (using Intel FPGA SDK for OpenCL), or Xilinx FPGAs (using Xilinx Vitis). The Controllers model integrates the use of different vendor specific technologies through different backends coordinated by the same runtime layer, effectively handling the architectural differences between different computing devices [52]. The programmer can write a single generic portable kernel code that can target different kinds of devices.…”

Section: Controllers Programming Modelmentioning

confidence: 99%

“…Each Controller object used in the program transparently leverages the native or vendor-specific programming model for the chosen device, such as CUDA or OpenCL, to perform these data transfers. This allows the skeleton to achieve data-transfer throughputs similar to those of the native or vendor-specific models [52]. If the tile to move is a sub-selection, appropriate data movements for only that specific part of the array are executed.…”

Section: Generation Of the Communication Patternmentioning

confidence: 99%

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EPSILOD: efficient parallel skeleton for generic iterative stencil computations in distributed GPUs

Castro

Santamaria-Valenzuela

Torres

et al. 2023

J Supercomput

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Iterative stencil computations are widely used in numerical simulations. They present a high degree of parallelism, high locality and mostly-coalesced memory access patterns. Therefore, GPUs are good candidates to speed up their computation. However, the development of stencil programs that can work with huge grids in distributed systems with multiple GPUs is not straightforward, since it requires solving problems related to the partition of the grid across nodes and devices, and the synchronization and data movement across remote GPUs. In this work, we present EPSILOD, a high-productivity parallel programming skeleton for iterative stencil computations on distributed multi-GPUs, of the same or different vendors that supports any type of n-dimensional geometric stencils of any order. It uses an abstract specification of the stencil pattern (neighbors and weights) to internally derive the data partition, synchronizations and communications. Computation is split to better overlap with communications. This paper describes the underlying architecture of EPSILOD, its main components, and presents an experimental evaluation to show the benefits of our approach, including a comparison with another state-of-the-art solution. The experimental results show that EPSILOD is faster and shows good strong and weak scalability for platforms with both homogeneous and heterogeneous types of GPU.

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Section: Controllers Programming Modelmentioning

confidence: 99%

Section: Generation Of the Communication Patternmentioning

confidence: 99%

EPSILOD: efficient parallel skeleton for generic iterative stencil computations in distributed GPUs

Castro

Santamaria-Valenzuela

Torres

et al. 2023

J Supercomput

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“…In Reference 7, the authors provided support for Controller to leverage Intel Stratix‐10 FPGAs as a target device. However, a major limitation was that full reconfiguration of the entire FPGA was required when mapping a task to the device, meaning that only one kernel could execute on the FPGA at any given time and as such it was common for the compute resource to be significantly under‐utilized.…”

Section: Background and Related Workmentioning

confidence: 99%

“…The work described in this article hides the complex and low‐level details associated with using DPR and synchronization mechanisms to support on‐the‐fly instantiation, stopping and resumption of kernels on specific parts of the FPGA fabric whilst the rest of the chip continues executing other workloads independently. In our approach, tasks are programmed as OpenCL kernels and managed with the controller model, 5‐7 which is a heterogeneous programming model implemented as a C99 library of functions. Controller aims to efficiently manage different types of devices with a portable interface and in this article we describe an extension to support multiple kernels and preemption on DPR capable FPGA systems.…”

Section: Introductionmentioning

confidence: 99%

Task‐based preemptive scheduling on FPGAs leveraging partial reconfiguration

Rodriguez-Canal

Brown

Torres

et al. 2023

Concurrency and Computation

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SummaryField‐programmable gate arrays (FPGAs) are an attractive type of accelerator for all‐purpose high performance computing computing systems due to the possibility of deploying tailored hardware on demand. However, the common tools for programming and operating FPGAs are still complex to use, especially in scenarios where diverse types of tasks should be dynamically executed. In this work, we present a programming abstraction with a simple interface that internally leverages high‐level synthesis, dynamic partial reconfiguration and synchronization mechanisms to use an FPGA as a multi‐tasking server with preemptive scheduling and priority queues. This leads to an improved use of the FPGA resources, allowing the execution of several different kernels concurrently and deploying the most urgent ones as fast as possible. The results of our experimental study show that our approach incurs only a 10 5% overhead in the worst case when using two reconfigurable regions, whilst providing a significant performance improvement of at least 24 21% over the traditional full reconfiguration approach.

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“…Além disso, encontrar uma amostra representativa de participantes experientes no domínio da programac ¸ão paralela é desafiador. Logo, o uso de métricas de codificac ¸ão bem estabelecidas na área de Engenharia de Software (e.g., Linhas de Código (LOC), Halstead e Constructive Cost Model -COCOMO) pode facilitar a avaliac ¸ão da produtividade [Adornes et al 2015, Griebler et al 2018, Miller et al 2018, Rodriguez-Canal et al 2021, Martínez et al 2022, Peccerillo e Bartolini 2022. Porém, nosso estudo anterior [Andrade et al 2021] mostrou limitac ¸ões, uma vez que estas métricas de codificac ¸ão não foram projetados para avaliar aplicac ¸ões paralelas.…”

Section: Introduc ¸ãOunclassified

Opinião de Brasileiros Sobre a Produtividade no Desenvolvimento de Aplicações Paralelas

Andrade

Griebler²,

Santos³

et al. 2022

Anais Do XXIII Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2022)

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A partir da popularização das arquiteturas paralelas, surgiram várias interfaces de programação a fim de facilitar a exploração de tais arquiteturas e aumentar a produtividade dos desenvolvedores. Entretanto, desenvolver aplicações paralelas ainda é uma tarefa complexa para desenvolvedores com pouca experiência. Neste trabalho, realizamos uma pesquisa para descobrir a opinião de desenvolvedores de aplicações paralelas sobre os fatores que impedem a produtividade. Nossos resultados mostraram que a experiência dos desenvolvedores é uma das principais razões para a baixa produtividade. Além disso, os resultados indicaram formas para contornar este problema, como melhorar e incentivar o ensino de programação paralela em cursos de graduação.

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Efficient heterogeneous programming with FPGAs using the Controller model

Cited by 8 publications

References 11 publications

EPSILOD: efficient parallel skeleton for generic iterative stencil computations in distributed GPUs

EPSILOD: efficient parallel skeleton for generic iterative stencil computations in distributed GPUs

Task‐based preemptive scheduling on FPGAs leveraging partial reconfiguration

Opinião de Brasileiros Sobre a Produtividade no Desenvolvimento de Aplicações Paralelas

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