Efficient Hardware Implementations of Low Bit Depth Motion Estimation Algorithms

Abstract

In this paper, we present efficient hardware implementation of multiplication free one-bit transform (MF1BT) based and constraint one-bit transform (C-1BT) based motion estimation (ME) algorithms, in order to provide low bit-depth representation based full search block ME hardware for real-time video encoding. We used a source pixel based linear array (SPBLA) hardware architecture for low bit depth ME for the first time in the literature. The proposed SPBLA based implementation results in a genuine data flow scheme which significantly reduces the number of data reads from the current block memory, which in turn reduces the power consumption by at least 50% compared to conventional 1BT based ME hardware architecture presented in the literature. Because of the binary nature of low bit-depth ME algorithms, their hardware architectures are more efficient than existing 8 bits/pixel representation based ME architectures.Index Terms-Low bit-depth motion estimation, motion estimation hardware, source pixel based linear arrays.

Software and Hardware Implementations of Stereo Matching

“…Early research work [50] only achieves non-video rate performance due to limited computing power [68]. Firstly implements software processing with low bit depth motion estimation algorithms for outdoor robot navigation [69].…”

A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation

“…The memory organization of the 1BT based ME hardware architectures proposed in [10] and [15] is shown in Figure 6. These architectures have an inefficient memory organization.…”

“…In [10], a motion vector (MV) based linear arrays hardware architecture is used for implementing 1BT based ME. In [15], a source pixel based linear arrays hardware architecture is used for implementing low bit depth ME algorithms proposed in [11] and [14]. In [16], a new sub-pixel accurate low bit depth ME algorithm and its hardware is presented.…”

“…The 1BT based ME hardware proposed in [10] and [15] cannot process 1920x1080 full HD videos in realtime. The Non-Match Counter architecture used in the proposed ME hardware is faster and has smaller area than the Non-Match Counter architecture used in the ME hardware proposed in [10] and [15].…”

“…The 1BT based ME hardware proposed in [10] and [15] cannot process 1920x1080 full HD videos in realtime. The Non-Match Counter architecture used in the proposed ME hardware is faster and has smaller area than the Non-Match Counter architecture used in the ME hardware proposed in [10] and [15]. Although the proposed ME hardware stores search windows of 4 MBs in on-chip memory, it uses less on-chip memory and it loads the on-chip memory from off-chip memory in less number of clock cycles than the ME hardware proposed in [10] and [15].…”