Efficient Hardware Implementation of Finite Field Arithmetic AB+C for Binary Ring-LWE Based Post-Quantum Cryptography

Abstract

Post-quantum cryptography (PQC) has gained significant attention from the community recently as it is proven that the existing public-key cryptosystems are vulnerable to the attacks launched from the well-developed quantum computers. The finite field arithmetic AB + C, where A and C are integer polynomials and B is a binary polynomial, is the key component for the binary Ring-learning-with-errors (BRLWE)-based encryption scheme (a low-complexity PQC suitable for emerging lightweight applications). In this paper, we propose a novel hardware implementation of the finite field arithmetic AB + C through three stages of interdependent efforts: (i) a rigorous mathematical formulation process is presented first; (ii) an efficient hardware architecture is then presented with detailed description; (iii) a thorough implementation has also been given along with the comparison. Overall, (i) the proposed basic structure (u = 1) outperforms the existing designs, e.g., it involves 55.9% less area-delay product (ADP) than [13] for n = 512; (ii) the proposed design also offers very efficient performance in time-complexity and can be used in many future applications.

KINA: Karatsuba Initiated Novel Accelerator for Ring-Binary-LWE (RBLWE)-based Post-Quantum Cryptography

“…While the comparison of area-time complexities listed in Table I is more on the theoretical side, there is a need for a more practical comparison. Thus, we have implemented the proposed accelerator on the Field-Programmable Gate Array (FPGA) platform and the experiment is setup as follows: (i) we have coded the proposed RBLWE-based PQC accelerator (KINA) with VHDL and have verified its functionality through ModelSim; (ii) we have synthesized and implemented the coded design on Xilinx FPGAs, i.e., Virtex-7 XC7V2000t and Kintex-7 XC7K325t devices, respectively, through Vivado 2020.2; (iii) we have $ : The authors of [29] have re-implemented the design in [24] (including all input processing shift-registers), we thus use the data from [29]. * : All the related calculation for all designs are based on the decryption phase of the RBLWE-based encryption scheme (Dec.: decryption).…”

“…But from the designed structure, maybe three q-bit n-size shift-registers are used (or multiple BRAMs) for [23]. Meanwhile, from the re-implemented result in [29], the design of [35] has two q-bit n-size shift-registers and one q-bit n-size output buffer.…”

“…The area-time complexities of the proposed designs (both the basic and higher-speed versions), in terms of the number of AND gates, XOR gates, adders, MUXes, and latency cycles, are listed in Table I along with those of the existing high-speed designs of [23], [24], [29]- [32], Note that the design of [27] is a special design based on LUT-like method and the structures of [26], [28] belong to compact designs, we thus do not list them here.…”

“…After the initial introduction [22], the authors reported the software implementation work on Atmel-AVR and ARM-Cortex-M0 microcontrollers. While on the hardware platform: (i) the first hardware implementation of the RBLWE-based scheme was released in [23]; (ii) the second hardware design for RBLWE-based PQC was reported in [24]; (iii) a high-speed hardware structure (but incomplete) was then reported in [25]; (iv) a compact RBLWE-based hardware architecture was presented in [26]; (v) a lookup-table (LUT)like method based hardware architecture was reported in [27]; (vi) another compact structure for RBLWE-based PQC was presented in [28]; (vii) a new high-speed hardware RBLWEbased structure was introduced in [29]; (viii) a pair of lowspeed and high-speed RBLWE-based hardware accelerators were presented in [30]; (ix) efficient hardware RBLWE-based architectures were also recently reported in [31], [32], respectively. Meanwhile, there also exist other types of implementations like the fault-resistant (software implementation) one of [33] and the fault detection scheme of [34] (based on the high-speed structure in [24]).…”

The Dichotomy of Neural Networks and Cryptography: War and Peace

“…It also serves to security-related scenarios such as information hiding [15], authentication [16,17], privacy [18], etc. Furthermore, cryptography is supported by a variety of enabling technologies and sciences including radix 2 n [19] and modular arithmetics [20], quantum computing [21,22], coding and information theory [23,24], Very Large Scale Integration [25], chaos theory [26], and error management techniques [27] are used to support cryptography.…”