2019 International Conference on Electrical, Computer and Communication Engineering (ECCE) 2019
DOI: 10.1109/ecace.2019.8679184
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Efficient Hardware Implementation of 256-bit ECC Processor Over Prime Field

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Cited by 10 publications
(14 citation statements)
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“…Concerning the aforementioned selections, several PM ECC designs exist in the literature; however, we preferred to include only those implemented and optimized for area-efficient realizations. Examples of the most recent hardware accelerators are available in [12][13][14][15][16][17][18]. A two-stage pipelined PM architecture of ECC is described in [12], where pipelining is utilized to decrease the critical path delay and carefully schedule the computations associated with PA and PD to reduce the number of clock cycles required; these two characteristics combine to decrease the time needed for a single PM operation, and the minimum utilization of area results in a higher throughput/area ratio.…”
Section: Low-area Hardware Implementations With Limitationsmentioning
confidence: 99%
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“…Concerning the aforementioned selections, several PM ECC designs exist in the literature; however, we preferred to include only those implemented and optimized for area-efficient realizations. Examples of the most recent hardware accelerators are available in [12][13][14][15][16][17][18]. A two-stage pipelined PM architecture of ECC is described in [12], where pipelining is utilized to decrease the critical path delay and carefully schedule the computations associated with PA and PD to reduce the number of clock cycles required; these two characteristics combine to decrease the time needed for a single PM operation, and the minimum utilization of area results in a higher throughput/area ratio.…”
Section: Low-area Hardware Implementations With Limitationsmentioning
confidence: 99%
“…An efficient hardware implementation of a 256 bit ECC processor over a GF(P) is presented in [14], where Jacobian coordinates have been utilized to avoid the costly modular inversion operation. In addition, an interleaved modular multiplier reduces the area and delay in modular multiplication.…”
Section: Low-area Hardware Implementations With Limitationsmentioning
confidence: 99%
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“…At present, the main means to solve the problem of information security is data encryption, mainly including RSA encryption system and elliptic curve encryption system. Elliptic Curve Cryptography (ECC) is a public-key encryption technology based on elliptic curve discrete logarithm problem, which was first proposed by Miller and Koblitz in 1985 [1] . Compared with RSA encryption system, elliptic curve encryption system has many advantages such as high encryption security, small amount of keys and high flexibility.…”
Section: Introductionmentioning
confidence: 99%
“…The whole protocol and process of data encryption and decryption in both SM2 and SM9 cryptographic algorithms are inseparable from the support of underlying modular operations, especially the modular inversion operation with the largest amount of computation and the longest time consumption [4] , which is the key to affect the execution efficiency of the entire cryptographic algorithm [5] . Rahman et al [1] used Jacobian coordinate transformation to compress the number of modular inversions required for point operations in ECC, but still could not avoid modular inversions. Rahman et al used the Jacobian coordinate transformation method to compress the number of modular inversions required for point operations in ECC, and designed a dedicated point multiplication architecture and a dedicated modular multiplier to improve the speed of the converted modular inversions, but still some of the modular inversions could not be converted, which directly affected the operation efficiency of the whole system.…”
Section: Introductionmentioning
confidence: 99%