Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs

Guglielmo, Giuseppe Di; Guglielmo, Luigi Di; Fummi, Franco; Pravadelli, Graziano

doi:10.1007/s10836-011-5209-8

Cited by 14 publications

(22 citation statements)

References 25 publications

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“…These transaction-based descriptions can model functional behaviors into transactions, but they are unable to describe cycle timing sequence of function behaviors. On the other hand, the FSM-based behavior specification, including FSM [12], EFSM [13][14][15], assignment decision diagram [16,17], and BDD [18], enables the description of cycle-accurate functional behaviors at the cost of exploring the whole state spaces and transitions, which limits the scale of design it can support.…”

Section: Related Workmentioning

confidence: 99%

Simulation-Based Hardware Verification with a Graph-Based Specification

Chen

Wang

2018

Mathematical Problems in Engineering

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Simulation-based verification continues to be the primary technique for hardware verification due to its scalability and ease of use; however, it lacks exhaustiveness. Although formal verification techniques can exhaustively prove functional correctness, they are limited in terms of the scale of their design due to the state-explosion problem. Alternatively, semiformal approaches can involve a compromise between scalability, exhaustiveness, and resource costs. Therefore, we propose an event-driven flow graph-based specification, which can describe the cycle-accurate functional behaviors without the exploration of whole state space. To efficiently generate input sequences according to the proposed specification, we introduce a functional automatic test pattern generation (ATPG) approach, which involves the proposed intelligent redundancy-reduction strategy to solve problems of random test vectors. We also proposed functional coverage criterion based on the formal specification to support a more reliable measure of verification. We implement a verification platform based on the proposed semiformal approach and compare the proposed semiformal approach with the constrained randomized test (CRT) approach. The experiment results show that the proposed semiformal verification method ensures a more exhaustive and effective exploration of the functional correctness of designs under verification (DUVs).

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Section: Related Workmentioning

confidence: 99%

Simulation-Based Hardware Verification with a Graph-Based Specification

Chen

Wang

2018

Mathematical Problems in Engineering

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“…Some papers address the problem of EFSM-based test generation [1,2,4,5]. If EFSMs are derived from HDL descriptions, such tests are able to achieve high level of code coverage and, as opposed to [3], to cope with state dependencies.…”

Section: Related Workmentioning

confidence: 99%

“…The EFSM formalism extends the classical FSM model by adding (1) input and output parameters, (2) registers and (3) transitions' guards and actions defined over registers and input parameters. The main idea is to clearly separate control and datapath (exactly as it is acknowledged in hardware design and synthesis).…”

Section: Introductionmentioning

confidence: 99%

“…The main idea is to clearly separate control and datapath (exactly as it is acknowledged in hardware design and synthesis). EFSM-based models are intensively used in functional test generation (to generate conformance test suites [1] or to cover unlikely corner cases [2]) as well as in formal verification, especially in model This work was supported in part by the Russian Foundation for Basic Research under grant 12-01-31343. checking (to check properties or to find errors and inconsistencies in a design model).…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Static analysis of HDL descriptions: Extracting models for verification

Kamkin¹,

Smolov²,

Melnichenko

2013

East-West Design &Amp; Test Symposium (EWDTS 2013)

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1The increasing complexity of hardware designs makes functional verification a challenge. The key issue of the state-of-the-art verification approaches is to obtain a "good" model for automated test generation or formal property checking. In this paper, we describe techniques for deriving EFSM-based models from HDL descriptions and briefly discuss applications of such models for verification. The distinctive feature of the suggested approach is that it automatically determines what registers of a design encode its state and use this information for model reconstruction.

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“…With the rapid increase in the complexity of circuits, it is important to ensure the correctness of circuits being designed [1][2][3]. In the procedure of circuit design, a hierarchical design technique is usually adopted, which include the following design steps: system behavioral specification, behavioral synthesis, register transfer level (RTL) description, logic synthesis, logic description, layout synthesis, layout, etc.…”

Section: Introductionmentioning

confidence: 99%

Determining Equivalent Signal Lines by Weight Value Assignment for Logic Verification of Digital Circuits

Zhang

Ling²,

Chen³

2014

TOEEJ

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Abstract:The VLSI technology has led to the increased complexity in hardward design, therefore the verification for the correctness of circuit operations has become an exrtremely important task. The verification procedure can be reduced by means of the equivalent signal lines in the circuits. In this paper, a new method is presented for determining the equivalent signal lines, the method utilizes the weight value assignment of signal lines in circuits. First of all, the method makes use of the topological information of circuits to perform forward weight value assignments, assign weight values to the signal lines from the primary inputs to primary outputs. Afterwards, carry out the backward weight value assignment, assign weight values to the signal lines from the primary outputs to primary inputs. Secondly, carry out the random pattern simulation to further check the equivalence of signal lines. A lot of experimental results show that the verification of digital circuits can be carried out effectively by using the method proposed in this paper, the time being needed for the verification procedure can be cut down by utilizing the equivalent signal lines.

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Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs

Cited by 14 publications

References 25 publications

Simulation-Based Hardware Verification with a Graph-Based Specification

Simulation-Based Hardware Verification with a Graph-Based Specification

Static analysis of HDL descriptions: Extracting models for verification

Determining Equivalent Signal Lines by Weight Value Assignment for Logic Verification of Digital Circuits

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