2019
DOI: 10.11591/eei.v8i2.1483
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Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures

Abstract: In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The digital delay is based on a Parallel Farrow Filter. Such architecture allows to reach a very high processing rate with wideband signals and it is suitable to be used with Time-Interleaved Analog to Digital Converters (TI-ADC). The proposed delay has been simulated in MATLAB, implemented on FPGA and characterized in terms of amplitude and phase response, maximum clock frequency and area.

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Cited by 5 publications
(3 citation statements)
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“…To make estimation of noise present in image and for removal of the same using complex algorithm is a crucial task which requires high computing capacity. In this context, hardware acceleration is crucial and Field programmable Gate Array (FPGA) best fit the growing demand of computational capabilities [8][9][10][11][12][13][14][15][16].…”
Section: Previous Work Donementioning
confidence: 99%
“…To make estimation of noise present in image and for removal of the same using complex algorithm is a crucial task which requires high computing capacity. In this context, hardware acceleration is crucial and Field programmable Gate Array (FPGA) best fit the growing demand of computational capabilities [8][9][10][11][12][13][14][15][16].…”
Section: Previous Work Donementioning
confidence: 99%
“…While in digital beamforming, the beamforming process is done using digital signal processing. Digital beamforming provides more flexibility and accuracy of the beamforming process in comparison to analog beamforming because it is easily to control the direction of beam through weight factors at baseband stage [14]. However, digital beamforming requires a separate transmit (receive) module dedicated to each antenna element, this module contains digital/analog converter analog to digital converter (ADC) or digital to analog converter (DAC), mixer, and power amplifier it is called RF chain.…”
Section: Introductionmentioning
confidence: 99%
“…The original general test equipment typically makes use of ARM or perhaps singlechip microcomputer because of the model and its particular math running ability will be gradual, as well as the energetic packing handle ability will be not enough [13][14][15][16][17][18][19][20][21][22][23][24][25][26]. For this finish, we created the common screening device depending on FPGA.…”
Section: Introductionmentioning
confidence: 99%