Efficient fault simulation through dynamic binary translation for dependability analysis of embedded software

A Survey of QEMU-Based Fault Injection Tools & Techniques for Emulating Physical Faults

“…Another method for abstracting various types of hardware failure models within QEMU is proposed in [49]. It defines a simulation environment that simulates hardware faults in early dependability analysis of embedded software (ESW) applications.…”

“…Nevertheless, the tool's accuracy in injecting faults in registers is shown to be good. This technique exhibits comparable characteristics in simulation runs from the perspective of dependability analysis accuracy compared to register-transfer level (RTL) failure simulation, but it is quicker, as demonstrated by experimental findings on bsearch, tcas, mandelbot, and dhrystone benchmark applications [49].…”

“…• Memory -The memory cells such as RAM and related parts are tested [44], [45], [46], [47], [50], [51], [54], [55], [63]. • Registers -General purpose and special purpose registers are tested in [44], [45], [48], [49], [50], [51], [53], [54], [58], and [66]. In addition to these components; instructions, network interfaces, controllers for the hard disk, USB, and network and block devices are tested.…”

“…• Transient [39], [48], [49], [53], [58], [63] • Intermittent [48], [58], [63] • Permanent [45], [48], [49], [50], [54], [58], [63], [66] faults. There are faults such as packet drop and packet modification [55], memory-state-aware faults [47], and faulty instructions [44] used by different tools.…”