Efficient error correction code configurations for quasi-nonvolatile data retention by DRAMs

Katayama, Y.; Negishi, Yoshinori; Morioka, Sumio

doi:10.1109/dftvs.2000.887158

Cited by 2 publications

(1 citation statement)

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“…The effects of ionizing radiation on memory chips have been extensively analyzed in the literature [6,29]. Several EDAC-based architectures have been proposed for hardening commercial DRAM memories [7,9,10,16,18]. Initially introduced in [4], the proposed approach relies on a memory architecture in which EDAC codes are utilized to address issues related to both permanent and transient faults.…”

Section: Architectural Considerationsmentioning

confidence: 99%

A Comparative Evaluation of Designs for Reliable Memory Systems

et al. 2005

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Abstract. This paper addresses the design of storage systems for operation under critical environmental conditions. For these applications, these systems should have low latency time in access, high performance in throughput and high storage capabilities; therefore, they must be assembled using highly reliable components, while allowing flexibility in design. Commercial Off The Shelf (COTS) components have often been used. A COTS-based architecture is analyzed in this paper; the proposed architecture uses design-level techniques (such as error detection/correction codes and scrubbing) to make commercially available Dynamic Random Access Memory (DRAM) chips tolerant to faults. This paper provides a complete and novel analysis of engineering alternatives which arise in the design of a highly reliable memory system based on Reed Solomon coding. A comparative analysis of methods for permanent fault detection is provided; moreover using a Markovian characterization, different functional arrangements (based on code and scrubbing frequency) are investigated and evaluated.

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