Efficient Encoding Architecture for IEEE 802.16e LDPC Codes

Kim, Jeong Ki; Yoo, Hyunseuk; Lee, Moon Ho

doi:10.1093/ietfec/e91-a.12.3607

Cited by 12 publications

(11 citation statements)

References 6 publications

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“…The blank in the table means that it is not given in the corresponding literature. In [7], the throughput of the encoder with code length of 648 under IEEE 802.11n is 360Mbps, while our encoder under the same condition has the throughput of 611Mbps. For WIMAX standard, although we consume more logic elements than [7] with code length of 2304, the throughput of our design is higher.…”

Section: Logic Elements Comparisons In Different Ratesmentioning

confidence: 85%

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QC-LDPC Encoder Structure for IEEE 802.16e/802.11n Standard

Wang¹,

Ge²,

Wang³

et al. 2016

IJCA

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Due to the popularity of LDPC (Low Density Parity Codes) in modern communication systems, there is a growing need of LDPC encoder with a faster encoding speed and more application compatibility. In this paper, an efficient QC-LDPC encoder architecture is proposed, which is suitable for both IEEE 802.16e standard and IEEE 802.11n standard. Owing to the special structure of multi-diagonal parity matrices, the inverse matrix is replaced with back substitution. Simplified RU algorithm is applied to the encoder structure, and the parallelism is determined by the row number of parity matrices in the two standards. The proposed architecture has full configurability with concern to code rate and code length. Simulation results confirm that the encoders work successfully from 1/2 rate to 5/6 rate under both two standards. To validate its feasibility, we have tested all code lengths of IEEE 802.11n standard and IEEE 806.12e standard. They all work accurately with the proposed encoder architecture, with the output throughputs ranging between 538 Mbps and 2879 Mbps.

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Section: Logic Elements Comparisons In Different Ratesmentioning

confidence: 85%

“…Efficient encoder structures were also designed for IEEE 802.16e and IEEE 802.11n in [7][8][9][10]. In paper [7], semi-parallel architecture was proposed and an encoder for QC-LDPC codes of the two standards was implemented. A joint design of encoder and decoder of LDPC codes was proposed based on FPGA platform [8].…”

Section: Introductionmentioning

confidence: 99%

QC-LDPC Encoder Structure for IEEE 802.16e/802.11n Standard

Wang¹,

Ge²,

Wang³

et al. 2016

IJCA

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“…Although the QC-LDPC encoder in [6] can provide 860 Mbps throughput, it is not rate compatible. The QC-LDPC encoder presented in [12] is capable of providing rate compatibility and high throughput up to 3.34 Gbps at 186 MHz clock frequency. In [14,15], the required number of clock cycles for encoding are presented instead of throughput.…”

Section: Proposed Low Complexity Cyclic Shiftermentioning

confidence: 99%

“…In many literatures, the encoders for QC-LDPC codes were presented [4][5][6][7][8][9][10][11][12][13]. The LDPC encoders presented in [4,5,[7][8][9][10][11] can support various code rates and codeword block lengths.…”

Section: Introductionmentioning

confidence: 99%

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7.7 Gbps Encoder Design for IEEE 802.11ac QC-LDPC Codes

Jung

Chung

Jung

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper proposes a high-throughput encoding process and encoder architecture for quasicyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

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Efficient Multi‐rate Encoder of QC‐LDPC Codes Based on FPGA for WIMAX Standard

Wang

et al. 2017

Chin. j. electron.

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Efficient Encoding Architecture for IEEE 802.16e LDPC Codes

Cited by 12 publications

References 6 publications

QC-LDPC Encoder Structure for IEEE 802.16e/802.11n Standard

QC-LDPC Encoder Structure for IEEE 802.16e/802.11n Standard

7.7 Gbps Encoder Design for IEEE 802.11ac QC-LDPC Codes

Efficient Multi‐rate Encoder of QC‐LDPC Codes Based on FPGA for WIMAX Standard

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