Efficient Design-for-Test Approach for Networks-on-Chip

Wang, Junshi; Ebrahimi, Masoumeh; Huang, Letian; Xie, Xuan; Li, Qiang; Li, Guangjun; Jantsch, Axel

doi:10.1109/tc.2018.2865948

Cited by 17 publications

(17 citation statements)

References 27 publications

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“…Wang et al [19] proposed an efficient design for the test technique of NoC. In this research work, Esy Test and comprehensive test scheme with minimized influence have been proposed to improve the system performance.…”

Section: Literature Surveymentioning

confidence: 99%

An Adaptive Arbitration Technique w ith 4x4 Mesh Topology f or Low Area a nd High Speed NOC Design

Salagala*,

Sharma,

Laxmanarayana

2020

IJITEE

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 Abstract: In recent days, On-Chip Communication is a major requirement in modern systems that produce efficient communication with less complexity and high throughput. Due to heavy traffic and increasing Network-On Chip (NoC) size, the routing algorithm produces poor performances. Normally, round-robin and matrix arbiters are used in NoC for high-speed switches. In this research work, three different types of arbiter algorithms are used such as priority algorithm, Time Division Multiplexed (TDM) algorithm, and Viterbi algorithm to improve the linearity of the NOC. Initially, the priority algorithm helps to minimize traffic congestion when the arbiter is in a busy mode. Second, the fairness and Quality of Service (QoS) of the NoC structure are analyzed by the TDM algorithm. Finally, the Viterbi algorithm based error prediction process is done in an NoC structure. Due to the usage of three proposed arbiter algorithms, the area of NoC can be reduced. The packet can be reached to the destination by using the arbitration process with less loss. In this research, the proposed methodology is called as Low Area-Fault-Tolerant Adaptive Arbitration based NoC architecture (LA-FTAA-NoC architecture). Finally, the Field Programmable Gate Array (FPGA) performance is evaluated such as LUT, flip flop, slices, and frequency in Spartan 6 hardware. In the proposed method, 2.42% of LUT, 3.1% of flip flop, and 8.63% of slices have reduced when compared to existing work.

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Section: Literature Surveymentioning

confidence: 99%

An Adaptive Arbitration Technique w ith 4x4 Mesh Topology f or Low Area a nd High Speed NOC Design

Salagala*,

Sharma,

Laxmanarayana

2020

IJITEE

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“…Apparently, the method requires interrupting the connection in order to start the test. Some other methods to test TSVs in a Network-on-Chip use existing techniques of wire testing [25]- [28]. With smart scheduling of these methods, we can even obtain uninterrupted testing that allows the system to maintain its operation during test.…”

Section: Related Workmentioning

confidence: 99%

“…Most works require partial or total preemption in order to test. Works for online NoC-testing in [25]- [28] perform with lower-bound of test periods around 16,000 to 50,000 while still degrading the system performance.…”

Section: Introductionmentioning

confidence: 99%

A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip

et al. 2020

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As one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs), Through-Silicon-Via (TSV) acts as the inter-layer link inside 3D Networks-on-Chip. However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To ensure the correctness of TSV connections at run-time, detecting multiple (clustering) defects is an important feature. While Error Correction Codes are limited by a certain number of detectable faults, using Built-In-Self-Test (BIST) prevents the system from operating normally during the test time. This paper first presents a Parity Product Code (PPC) with the ability to correct one fault and detect, at least, two faults. Second, we present extended PPC (EPPC) to detect multiple defects within the links of Networks-on-Chip by using two or more additional matrices. Furthermore, we present the distance-aware version of EPPC to detect multiple defects by using only one extra matrix. The results show that the distance-aware EPPC can detect 100% of clustering defects and multiple random defects within two and three cycles, respectively. The performance evaluation for Networkon-Chip testing also shows no degradation while providing an extremely short response time (2-3 cycles). INDEX TERMS 3D-ICs, fault-tolerance, error correction code, through-silicon-via, product code, parity check, networks-on-chip, fault-detection.

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“…The resilient NoC router evaluates the area and power overhead with a different application mechanism under error conditions. Wang et al [19] highlights the BIST (Built-in-self-Test) based NoC to improve the reliability. The quick fault detection and affected data packet detection are achieved using BIST.…”

Section: Literature Reviewmentioning

confidence: 99%

Design of an Efficient Fault and Congestion Free NoC Design using Adaptive Routing on FPGA

S.P*¹,

B.S²

2019

IJRTE

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Manufacturing fault-free System on Chips (SoCs) with performance scaling is a challenging task. The Network on Chip (NoC) architecture offers scalability and reliability to the SoC designs. In this paper, the fault detection and correction mechanism for a congestion-free Router architecture along with Mesh-NoC for different sizes are discussed. The proposed hardware architecture of NoC-Router includes Input registers (which store five -port inputs with Fault injection), Error Correction Code (that encodes the input data) followed by packet formation with Arbitration mechanism (that grants the permission to priority based encoder). The prior packet data is input to the adaptive-XY routing and it operates with the various congestion issues on choosing the shortest route. The detection and correction of the faulty bits from the network are monitored by ECC decoder. This NoC router can tolerate transient fault; provides low-latency and high throughput performance for all MPSoC applications. The Normal –XY Routing algorithm is incorporated in same router for comparison purpose. The synthesis results includes chip area, and maximum operating frequency over Artix-7 FPGA technology. Outcomes are tabulated and they show a marked improvement over previous cases. The performance evaluation is considered in terms of average latency and maximum throughput at different input traffic. It’s analyzed for novelty features as well.

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Efficient Design-for-Test Approach for Networks-on-Chip

Cited by 17 publications

References 27 publications

An Adaptive Arbitration Technique w ith 4x4 Mesh Topology f or Low Area a nd High Speed NOC Design

An Adaptive Arbitration Technique w ith 4x4 Mesh Topology f or Low Area a nd High Speed NOC Design

A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip

Design of an Efficient Fault and Congestion Free NoC Design using Adaptive Routing on FPGA

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