ACM SIGGRAPH 2007 Courses 2007
DOI: 10.1145/1281500.1281565
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Efficient data reduction and cache-coherent techniques toward real-time performance

Abstract: Figure 1: Application of our multi-resolution techniques and cache-efficient layouts to the rendering of the double eagle tanker (82 million triangles). By using these techniques, we are able to significantly improve the performance over the previous rasterization techniques and achieve an interactive performace on a commodity hardware. The performance improvement is mainly achieved by the significant reduction on the amount of necessary data and cache-coherent access patterns on the data. Course Notes: State-… Show more

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Cited by 2 publications
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“…On a higher algorithmic level, it also involves designing cache aware or cache oblivious data structures and algorithms (see e.g. [YM06, Kas07]). Also, multi‐core CPUs and parallel programming methods can be utilized to give our methods a further performance boost.…”
Section: Discussionmentioning
confidence: 99%
“…On a higher algorithmic level, it also involves designing cache aware or cache oblivious data structures and algorithms (see e.g. [YM06, Kas07]). Also, multi‐core CPUs and parallel programming methods can be utilized to give our methods a further performance boost.…”
Section: Discussionmentioning
confidence: 99%