Proceedings of the Great Lakes Symposium on VLSI 2017 2017
DOI: 10.1145/3060403.3060468
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Efficient Critical Path Selection Under a Probabilistic Delay Model

Ahish Mysore Somashekar
1
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Spyros Tragoudas
2
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Cited by 5 publications
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Test set identification for improved delay defect coverage in the presence of statistical delays

Javvaji
1
,
Shanyour
2
,
Tragoudas
3
2018
2018 19th International Symposium on Quality Electronic Design (ISQED)
3
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1
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Test set identification for improved delay defect coverage in the presence of statistical delays

Javvaji
1
,
Shanyour
2
,
Tragoudas
3
2018
2018 19th International Symposium on Quality Electronic Design (ISQED)
3
0
1
0
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NBTI and HCI Aging Prediction and Reliability Screening During Production Test

Yu
1
,
Ren
2
,
Lu
3
et al. 2020
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
10
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3
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On the Sensitization Probability of a Critical Path Considering Process Variations and Path Correlations

Javvaji
1
,
Tragoudas
2
2019
IEEE Trans. VLSI Syst.
1
0
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