Efficient control flow restructuring for GPUs

Reißmann, Nico; Falch, Thomas L.; Bjørnseth, Benjamin Andreassen; Bahmann, Helge; Meyer, Jan Christian; Jahre, Magnus

doi:10.1109/hpcsim.2016.7568315

Cited by 10 publications

(7 citation statements)

References 21 publications

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“…As discussed above, branch divergence takes both costs of the true and false sides of a divergent branch to execute it, so that it decreases execution efficiency of GPU programs. Several methods have been proposed to reduce branch divergence and improve execution efficiency [19], [20], [21], [22], [23], [24], [25]. On the other hand, some traditional optimizations may increase branch divergence and decrease execution efficiency.…”

Section: Branch Divergencementioning

confidence: 99%

“…In addition, it does not duplicate code, so that it incurs only a linear increase in the number of basic blocks. Reissmann et al [24] proposed control flow restructuring technique that consists of loop restructuring and branch restructuring. Loop restructuring converts all loops to tail-controlled loops, and branch restructuring ensures proper nesting of control flow.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Scalar Replacement Considering Branch Divergence

Fukuhara

Takimoto

2022

Journal of Information Processing

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GPU with the Single Instruction Multiple Data (SIMD) execution model enables a program to work efficiently. However, the efficiency may decrease because of branch divergence that occurs when SIMD threads follow different paths in some branches. Once the divergence occurs, some threads must wait until completion of the execution of the others. Thus, it is important to reduce branch divergence to improve the efficiency of GPU programs. On the other hand, branch divergence may be increased by some traditional code optimizations based on code motion such as partial redundancy elimination (PRE) and scalar replacement (SR). These methods insert some expressions into some paths, on which insertion points may be included in divergent branches. That is, the insertion may increase branch divergence, which may result in the decrease of execution efficiency of GPU programs. In this paper, we propose a new SR approach, called Speculative SR based on Question Propagation (SSRQP), which not only removes redundant memory accesses but also reduces branch divergence. SSRQP achieves SR based on speculative code motion, which not only eliminates inter-iteration redundant memory accesses without increasing branch divergence but also decreases branch divergence that originally exists through hoisting memory accesses in true and false sides of a divergent branch out of it. To prove the effectiveness of our method, we have conducted experiments through applying it to some benchmarks with divergent branches. The experimental results show that it can improve the efficiency about 40% in the best case in comparison with traditional techniques.

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Section: Branch Divergencementioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Scalar Replacement Considering Branch Divergence

Fukuhara

Takimoto

2022

Journal of Information Processing

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“…nodes in -regions, i.e., control flow equivalent to if-then-else, switch, and do-while statements, while PCFR can recover arbitrary complex control flow, i.e., control flow that is not restricted to RVSDG constructs. PCFR reduces the number of static branches in the resulting control flow [3], but might also result in undesirable control flow for certain architectures, such as graphic processing units [36]. For the sake of brevity, we omit a discussion of SCFR and PCFR as the algorithms are extensively described by Bahmann et al [3].…”

Section: Intra-procedural Control Flowmentioning

confidence: 99%

RVSDG

Reißmann

Meyer

Bahmann³

et al. 2020

ACM Trans. Embed. Comput. Syst.

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Intermediate Representations (IRs) are central to optimizing compilers as the way the program is represented may enhance or limit analyses and transformations. Suitable IRs focus on exposing the most relevant information and establish invariants that different compiler passes can rely on. While control-flow centric IRs appear to be a natural fit for imperative programming languages, analyses required by compilers have increasingly shifted to understand data dependencies and work at multiple abstraction layers at the same time. This is partially evidenced in recent developments such as the Multi-Level Intermediate Representation (MLIR) proposed by Google. However, rigorous use of data flow centric IRs in general purpose compilers has not been evaluated for feasibility and usability as previous works provide no practical implementations. We present the Regionalized Value State Dependence Graph (RVSDG) IR for optimizing compilers. The RVSDG is a data flow centric IR where nodes represent computations, edges represent computational dependencies, and regions capture the hierarchical structure of programs. It represents programs in demand-dependence form, implicitly supports structured control flow, and models entire programs within a single IR. We provide a complete specification of the RVSDG, construction and destruction methods, as well as exemplify its utility by presenting Dead Node and Common Node Elimination optimizations. We implemented a prototype compiler and evaluate it in terms of performance, code size, compilation time, and representational overhead. Our results indicate that the RVSDG can serve as a competitive IR in optimizing compilers while reducing complexity.

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“…SCFR recovers only control flow that resembles the structural nodes in λ-regions, i.e., control flow equivalent to if-then-else, switch, and do-while statements, while PCFR can recover arbitrary complex control flow, i.e., control flow that is not restricted to RVSDG constructs. PCFR reduces the number of static branches in the resulting control flow [3], but might also result in undesirable control flow for certain architectures, such as graphic processing units [33]. For the sake of brevity, we omit a discussion of SCFR and PCFR as the algorithms are extensively described by Bahmann et al [3].…”

Section: Intra-procedural Control Flow Recoverymentioning

confidence: 99%

RVSDG: An Intermediate Representation for Optimizing Compilers

Reissmann,

Meyer,

Bahmann

et al. 2019

Preprint

Self Cite

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Intermediate Representations (IRs) are central to optimizing compilers as the way the program is represented may enhance or limit analyses and transformations. Suitable IRs focus on exposing the most relevant information and establish invariants that different compiler passes can rely on. While control-flow centric IRs appear to be a natural fit for imperative programming languages, analyses required by compilers have increasingly shifted to understand data dependencies and work at multiple abstraction layers at the same time. This is partially evidenced in recent developments such as the MLIR proposed by Google for deep learning. However, rigorous use of data flow centric IRs in general purpose compilers has not been evaluated for feasibility and usability as previous works provide no practical implementations.We present the Regionalized Value State Dependence Graph (RVSDG) IR for optimizing compilers. The RVSDG is a data flow centric IR where nodes represent computations, edges represent computational dependencies, and regions capture the hierarchical structure of programs. It represents programs in demand-dependence form, implicitly supports structured control flow, and models entire programs within a single IR. We provide a complete specification of the RVSDG, construction and destruction methods, as well as exemplify its utility by presenting Dead Node and Common Node Elimination optimizations. We implemented a prototype compiler and evaluate it in terms of performance, code size, compilation time, and representational overhead. Our results indicate that the RVSDG can serve as a competitive IR in optimizing compilers while reducing complexity.

show abstract

Efficient control flow restructuring for GPUs

Cited by 10 publications

References 21 publications

Scalar Replacement Considering Branch Divergence

Scalar Replacement Considering Branch Divergence

RVSDG

RVSDG: An Intermediate Representation for Optimizing Compilers

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