Efficient Conflict Analysis for Finding All Satisfying Assignments of a Boolean Circuit

Abstract

Finding all satisfying assignments of a propositional formula has many applications to the synthesis and verification of hardware and software. An approach to this problem that has recently emerged augments a clause-recording propositional satisfiability solver with the ability to add "blocking clauses." One generates a blocking clause from a satisfying assignment by taking its complement. The resulting clause prevents the solver from visiting the same solution again. Every time a blocking clause is added the search is resumed until the instance becomes unsatisfiable. Various optimization techniques are applied to get smaller blocking clauses, since enumerating each satisfying assignment would be very inefficient. In this paper, we present an improved algorithm for finding all satisfying assignments for a generic Boolean circuit. Our work is based on a hybrid SAT solver that can apply conflict analysis and implications to both CNF formulae and general circuits. Thanks to this capability, reduction of the blocking clauses can be efficiently performed without altering the solver's state (e.g., its decision stack). This reduces the overhead incurred in resuming the search. Our algorithm performs conflict analysis on the blocking clause to derive a proper conflict clause for the modified formula. Besides yielding a valid, nontrivial backtracking level, the derived conflict clause is usually more effective at pruning the search space, since it may encompass both satisfiable and unsatisfiable points. Another advantage is that the derived conflict clause provides more flexibility in guiding the score-based heuristics that select the decision variables. The efficiency of our new algorithm is demonstrated by our preliminary results on SAT-based unbounded model checking of VIS benchmark models. Work supported in part by SRC contract 2004-TJ-920.

SMT Techniques for Fast Predicate Abstraction

“…As pointed out in [JHS05], for Chaff's DPLL procedure this result easily follows from the proofs in [ZM03]. For essentially any practical DPLL strategy or variant, it follows from [NOT05], where the termination proof uses a wellfounded ordering on DPLL search states, based on a lexicographic comparison of the number of literals in each decision level.…”

Prime clauses for fast enumeration of satisfying assignments to boolean circuits

“…• Case A : without pruning, with greedy minimization The implementations of cases C and D use the incremental SAT, while case B is the algorithm of [6]. Table 1 compares the numbers of pre-image steps that can be completed in a given amount of time; '*' after the number of pre-image steps indicates that convergence was not reached.…”

“…The minimization algorithm based on lifting variables generates prime blocking clauses that prune out more search space in concert with the pruning algorithm of [6]. Experimental results show a very significant improvement in the speed of AllSAT solving and a dramatic one in the number of blocking clauses that make up the solution (data not shown for lack of space).…”

Prime clauses for fast enumeration of satisfying assignments to Boolean circuits

“…In [8] the author builds an auxiliary implication graph to find a subset of the input assignments sufficient to justify the output of the circuit. Our previous work [6] improves on this approach by performing an additional conflict analysis on each blocking clause.…”

“…For lack of space, we refer the reader to [6] for a discussion of related work. We only mention here that recently [5] proposed to represent the set of satisfying assignments as circuits.…”