Efficient conditional operations for data-parallel architectures

Kapasi, Ujval J.; Dally, William J.; Rixner, Scott; Mattson, Peter; Owens, John D.; Khailany, Brucek

doi:10.1145/360128.360145

Cited by 58 publications

(20 citation statements)

References 12 publications

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“…Smith et al also provide a good summary of performance comparisons among various vector ISAs that incorporate conditional operations. An idea similar to the above was developed for stream processors by Kapasi et al [17].…”

Section: Related Workmentioning

confidence: 99%

CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures

Rhu¹,

Erez²

2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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Wide SIMD-based GPUs have evolved into a promising platform for running general purpose workloads. Current programmable GPUs allow even code with irregular control to execute well on their SIMD pipelines. To do this, each SIMD lane is considered to execute a logical thread where hardware ensures that control flow is accurate by automatically applying masked execution. The masked execution, however, often degrades performance because the issue slots of masked lanes are wasted. This degradation can be mitigated by dynamically compacting multiple unmasked threads into a single SIMD unit. This paper proposes a fundamentally new approach to branch compaction that avoids the unnecessary synchronization required by previous techniques and that only stalls threads that are likely to benefit from compaction. Our technique is based on the compaction-adequacy predictor (CAPRI). CAPRI dynamically identifies the compactioneffectiveness of a branch and only stalls threads that are predicted to benefit from compaction. We utilize a simple single-level branch-predictor inspired structure and show that this simple configuration attains a prediction accuracy of 99.8% and 86.6% for non-divergent and divergent workloads, respectively. Our performance evaluation demonstrates that CAPRI consistently outperforms both the baseline design that never attempts compaction and prior work that stalls upon all divergent branches.

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Section: Related Workmentioning

confidence: 99%

CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures

Rhu¹,

Erez²

2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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“…Purcell et al [5] have presented an implementation of bitonic merge sort on GPUs based on an implementation by Kapasi et al [6]. Kipfer et al [7,8] have shown an improved version of the bitonic sort as well as an odd-even merge sort.…”

Section: Introductionmentioning

confidence: 99%

A Practical Quicksort Algorithm for Graphics Processors

Cederman

Tsigas

2008

Algorithms - ESA 2008

121

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Abstract. In this paper we present GPU-Quicksort, an efficient Quicksort algorithm suitable for highly parallel multi-core graphics processors. Quicksort has previously been considered as an inefficient sorting solution for graphics processors, but we show that GPU-Quicksort often performs better than the fastest known sorting implementations for graphics processors, such as radix and bitonic sort. Quicksort can thus be seen as a viable alternative for sorting large quantities of data on graphics processors.

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“…Note that in this algorithm, conditional input and output streams are used to selectively fetch the correct number of row elements and properly output the result only when the row computation is complete. Since the kernel language has extremely restricted conditional syntax, conditional streaming [13] allows a number of important operations, such as handling data-dependent control constructs, merging or appending streams, and limited load balancing.…”

Section: Imagine Implementationmentioning

confidence: 99%