Efficient computation of canonical form for boolean matching in large libraries

Debnath, Debatosh; Sasao, Tsutomu

doi:10.1109/aspdac.2004.1337660

Cited by 21 publications

(24 citation statements)

References 19 publications

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“…Previous work on Boolean matching differs from the proposed algorithm in that (a) it targets large functions [2], (b) it is inherently BDD-based and therefore not nearly as fast [3][6], (c) it is limited to only permutation of inputs without considering their complementation [10], (d) it is not scalable due to high computational complexity of some computations, such as implicant table generation [8] [9]. This paper presents two algorithms: a fast heuristic one and a slower nearly-exact one.…”

Section: Introductionmentioning

confidence: 99%

Fast Boolean matching based on NPN classification

Huang

Wang

Nasikovskiy

et al. 2013

2013 International Conference on Field-Programmable Technology (FPT)

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Abstract-This paper proposes a fast algorithm for Boolean matching of completely specified Boolean functions. The algorithm is based on the NPN classification and can be applied on-the-fly to millions of small practical functions appearing in industrial designs, leading to runtime and memory reduction in logic synthesis and technology mapping. The algorithm is conceptually simpler, faster, and more scalable than previous work. I. IntroductionAn NPN class is a set of Boolean functions derived from each other by permuting and complementing the inputs, and complementing the output. Boolean matching determines whether two Boolean functions belong to the same NPN class. In the practical applications, Boolean matching is used to match a function against a library of functions whose implementation or other properties are known or have been pre-computed.AIG This paper presents two algorithms: a fast heuristic one and a slower nearly-exact one. They are compared against [8] believed to be state-of-the-art in Boolean matching on a large set of small practical functions derived from industrial designs. The conclusion is that the proposed heuristic algorithm is often faster without degrading quality, while a more elaborate nearly-exact algorithm computes fewer classes than [8]. Moreover, [8] cannot be applied to functions of more than 9 inputs, which limits its practicality. Meanwhile, the proposed algorithm scales to 16 variables and is therefore a better fit for cut-based logic synthesis and technology mapping.The rest of the paper is organized as follows: Section II contains relevant background. Section III describes the proposed three-step algorithm. Section IV shows experimental results. Section V concludes the paper.

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Section: Introductionmentioning

confidence: 99%

Fast Boolean matching based on NPN classification

Huang

Wang

Nasikovskiy

et al. 2013

2013 International Conference on Field-Programmable Technology (FPT)

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“…[6] improves the approach by pruning the search tree, using signatures (including first order cofactors) and symmetry checks. These approaches are slower than canonical form based methods [1], except for very small numbers of input variables, but their main drawback is the large memory requirements, which effectively limit its applicability to functions with up to a maximum of dozen variables [6], [9]. Canonical form-based approaches, on the other hand, scales well up to over twenty input variables.…”

Section: Related Workmentioning

confidence: 99%

“…Finally, other approaches such as [6], [9] rely on a preliminary exploration of the function space that allows the precomputation of minterm positions. This information is then saved into huge lookup tables.…”

Section: Related Workmentioning

confidence: 99%

A Transform-Parametric Approach to Boolean Matching

Agosta

Bruschi

Pelosi

et al. 2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we face the problem of P-equivalence Boolean matching. We outline a formal framework that unifies some of the spectral and canonical form-based approaches to the problem.As a first major contribution, we show how these approaches are particular cases of a single generic algorithm, parametric with respect to a given linear transformation of the input function.As a second major contribution, we identify a linear transformation that can be used to significantly speed up Boolean matching with respect to the state of the art. Experimental results show that, on average, our approach is five times faster than the main competitor on 20-variables input functions, and scales better, allowing to match even larger components.

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“…Recall from Section 2.5, that two functions INTEGRATED TECHNOLOGY MAPPING algorithm OptimalDelayCover(v, P) /* v is a graph vertex, P is set of library patterns */ for u ∈ f anin(v) do OptimalDelayCover(u, P) for γ ∈ Γ(v) do /* Γ(v) is the set of possible load intervals at v */ cost(v, γ) : are NPN-equivalent if one can be obtained from the other by negation and/or permutation of the inputs and outputs. The dominant approach for Boolean matching is to compute for each library cell a canonical (or semi-canonical) form that is an invariant with respect to input/output and store it in a hash table [145,146,147,148,149]. To attempt a match for a subgraph, the matcher computes the canonical form for the associated function and looks it up in a hash table.…”

Section: Technology Mappingmentioning

confidence: 99%

Integrated logic synthesis using simulated annealing

Färm

Dubrova

Kuehlmann

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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KTH School of Information andCommunication Technology SE-164 40 Kista SWEDEN Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i elektronik fredagen den 26 januari 2007 klockan 9.00 i Sal E, Forumhuset, Kungl Tekniska högskolan, Isafjordsgatan 39, Kista. © Petra Färm, januari 2007Tryck: Universitetsservice US AB iii Abstract A conventional logic synthesis flow is composed of three separate phases: technology independent optimization, technology mapping, and technology dependent optimization. A fundamental problem with such a three-phased approach is that the global logic structure is decided during the first phase without any knowledge of the actual technology parameters considered during later phases. Although technology dependent optimization algorithms perform some limited logic restructuring, they cannot recover from fundamental mistakes made during the first phase, which often results in non-satisfiable solutions.We present a global optimization approach combining technology independent optimization steps with technology dependent objectives in an annealing-based framework. We prove that, for the presented move set and selection distribution, detailed balance is satisfied and thus the annealing process asymptotically converges to an optimal solution. Furthermore, we show that the presented approach can smoothly trade-off complex, multiple-dimensional objective functions and achieve competitive results. The combination of technology independent and technology dependent objectives is handled through dynamic weighting. Dynamic weighting reflects the sensitivity of the local graph structures with respect to the actual technology parameters such as gate sizes, delays, and power levels. The results show that, on average, the presented advanced annealing approach can improve the area and delay of circuits optimized using the Boolean optimization technique provided by SIS with 11.2% and 32.5% respectively.Furthermore, we demonstrate how the developed logic synthesis framework can be applied to two emerging technologies, chemically assembled nanotechnology and molecule cascades. New technologies are emerging because a number of physical and economic factors threaten the continued scaling of CMOS devices. Alternatives to silicon VLSI have been proposed, including techniques based on molecular electronics, quantum mechanics, and biological processes. We are hoping that our research in how to apply our developed logic synthesis framework to two of the emerging technologies might provide useful information for other designers moving in this direction.iv

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Efficient computation of canonical form for boolean matching in large libraries

Cited by 21 publications

References 19 publications

Fast Boolean matching based on NPN classification

Fast Boolean matching based on NPN classification

A Transform-Parametric Approach to Boolean Matching

Integrated logic synthesis using simulated annealing

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