Efficient co-design partitioning of WLANs on SoC-based SDRs

Akeela, Rami; Elziq, Yacoub

doi:10.1007/s00542-019-04641-7

Cited by 2 publications

(1 citation statement)

References 37 publications

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“…Standalone embedded SDRs are based on SoC [5], [6] or custom multiprocessor architectures based on Network On Chips (NoC) [7]. If it allows portability and flexibility, it also leads to energy consumption several orders of magnitude higher than the requirements for IoT end-devices [8]. On the other side, there are also very cheap SDR such as RTL-SDR [9], but these devices have limited bandwidth, limited targetable carrier frequencies, and require processing to be done on an external computing unit.…”

Section: Introductionmentioning

confidence: 99%

LOLA SDR: Low Power Low Latency Software Defined Radio for Broadcast Audio Applications

Etrillard¹,

Gerzaguet

Feichter³

et al. 2023

IEEE Trans. Circuits Syst. II

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This brief proposes a new low power, low latency and low cost reconfigurable architecture for software defined radio. Due to their flexibility and reconfigurability, software defined radios are now massively used as wideband transceivers, channel sounders or network gateways. However, they often struggle to meet the desired requirements in terms of energy consumption and throughput. In this brief, we present a new architecture capable of tackling these challenges, by combining an off-the-shelf generic radio component with a low power microcontroller associated to a Fourier transform coprocessor. To prove the benefit of our approach, after describing the key assets of the architecture, we derive a complete physical layer dedicated to audio broadcast applications. This chain is capable of streaming High Definition audio stream in real time with low power (437 mW) and very low latency (854 µs). We show that our processing chain can be flawlessly run on our architecture paving the way for larger adoption of a new generation of low power low latency software defined radio architectures.

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