Efficient CMOS Invertible Logic Using Stochastic Computing

Smithson, Sean C.; Onizawa, Naoya; Meyer, Brett H.; Gross, Warren J.; Hanyu, Takahiro

doi:10.1109/tcsi.2018.2889732

Cited by 54 publications

(61 citation statements)

References 22 publications

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“…For example, an invertible multiplier (forward) and factorizer (backward) was implemented using a Boltzmann machine using a standard CMOS process [92]. Recent results have demonstrated a CMOS chip that implements neural inference (forward) and training (backward) in the same hardware with invertible logic [90].…”

Section: B Low-complexity Trainingmentioning

confidence: 99%

Hardware-Aware Design for Edge Intelligence

Gross

Meyer

Ardakani

2021

IEEE Open J. Circuits Syst.

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Section: B Low-complexity Trainingmentioning

confidence: 99%

Hardware-Aware Design for Edge Intelligence

Gross

Meyer

Ardakani

2021

IEEE Open J. Circuits Syst.

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“…An operation of nodes can be approximated by CMOS devices for implementation on FPGAs or ASICs with stochastic computing [18]. Stochastic computing represents real values as frequencies of '1' in stochastic bit streams [24].…”

Section: B Circuit Design Using Stochastic Computingmentioning

confidence: 99%

“…To implement the CMOS invertible logic circuit that computes the convolutional layer, the convolutional function should be converted to the Hamiltonian; however, only a function that is represented by combinational logic can be converted to the Hamiltonian. For example, functions implemented in the invertible logic circuit can be represented by combinational logic in [18] and [19]. To convert the convolutional function to the Hamiltonian, the sequential process should be represented by combinational logic.…”

Section: Design Of the Hamiltonian To Train The Bcnn A Hamiltonimentioning

confidence: 99%

“…The binary multiplication is implemented to a computation block that consists of four XNOR gates, a 4-input bit counter and a threshold function. The Hamiltonian of this computation block is composed of a combination of small Hamiltonians that are obtained from components in the computation block such as the XNOR gate, and the mechanism of combining H is described in [18]. In the case of Fig.…”

Section: B Hamiltonian Design Of a 2-layer Bcnnmentioning

confidence: 99%

“…Invertible logic provides a capability for probabilistic bidirectional operations (forward and backward modes) [14] using a nanomagnetic device model [15] and a Boltzmann machine [16]. The device model can be implemented by a magnetic tunnel junctions [17] or approximated by stochastic computing that represents CMOS invertible logic [18]. In our previous study, the hardware implementation of CMOS invertible logic was limited to training hardware for a single binarized perceptron [19].…”

Section: Introductionmentioning

confidence: 99%

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Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic

et al. 2020

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In this paper, we implement fast and power-efficient training hardware for convolutional neural networks (CNNs) based on CMOS invertible logic. The backpropagation algorithm is generally hard to implement in hardware because it requires high-precision floating-point arithmetic. Even though parameters of CNNs can be represented by fixed points or even binary during inference, it is still represented by floating points during training. Our hardware uses low-precision data representation for both inference and training. For hardware implementation, we exploit CMOS invertible logic for training. The use of invertible logic enables logic circuits to compute probabilistic bidirectional operation (forward and backward modes) and can be implemented by stochastic computing. The proposed hardware obtains parameters of neural networks such as weights directly from given data (an input feature map and a true label) without backpropagation. For performance evaluation, the proposed hardware is implemented on an FPGA and trains a binarized 2-layer convolutional neural network model using a modified MNIST dataset. This implementation shows an energy efficiency improvement of approximately 134x compared to that of a CPU implementation that executes the training of the same model as that used in the proposed hardware. Training on the proposed hardware is approximately 40x faster than training on the CPU using the backpropagation algorithm while maintaining almost the same cognition accuracy. INDEX TERMS CMOS invertible logic, Neural network, Stochastic computing.

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A Monolithic Stochastic Computing Architecture for Energy Efficient Arithmetic

et al. 2022

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As the energy and hardware investments necessary for conventional high‐precision digital computing continue to explode in the era of artificial intelligence (AI), a change in paradigm that can trade precision for energy and resource efficiency is being sought for many computing applications. Stochastic computing (SC) is an attractive alternative since, unlike digital computers, which require many logic gates and a high transistor volume to perform basic arithmetic operations such as addition, subtraction, multiplication, sorting, etc., SC can implement the same using simple logic gates. While it is possible to accelerate SC using traditional silicon complementary metal–oxide–semiconductor (CMOS) technology, the need for extensive hardware investment to generate stochastic bits (s‐bits), the fundamental computing primitive for SC, makes it less attractive. Memristor and spin‐based devices offer natural randomness but depend on hybrid designs involving CMOS peripherals for accelerating SC, which increases area and energy burden. Here, the limitations of existing and emerging technologies are overcome, and a standalone SC architecture embedded in memory and based on 2D memtransistors is experimentally demonstrated. The monolithic and non‐von‐Neumann SC architecture occupies a small hardware footprint and consumes a miniscule amount of energy (<1 nJ) for both s‐bit generation and arithmetic operations, highlighting the benefits of SC.

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Efficient CMOS Invertible Logic Using Stochastic Computing

Cited by 54 publications

References 22 publications

Hardware-Aware Design for Edge Intelligence

Hardware-Aware Design for Edge Intelligence

Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic

A Monolithic Stochastic Computing Architecture for Energy Efficient Arithmetic

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