Efficient CIC‐based architecture with improved aliasing rejection and reduced computational complexity

Abstract

A useful cascaded integrator comb (CIC)-based architecture is presented that improves the worst-case alias rejection of the CIC filter and simultaneously reduces the computational load of its integration section. Since regularity and simplicity are acceptably preserved, the proposed design outperforms other recent CIC-based architectures from literature where these two desirable characteristics are severely affected.

Decimation filters with minimum number of additions per output sample

“…Example 2: In this example, we compare the filter from Figure 4 with classic CIC filter [1], multistage filters [2][3][4], and single-stage sharpened filter [7]. Table 2 shows the maximum passband deviation, minimum folding-band attenuation, and the number of APOS of these filters.…”

“…Such an approach is utilized in multistage decimation filters. State-of-the-art methods for their design usually consider two stages [2][3][4][5][6]. This Letter proposes a framework for the design of multistage decimation filters with minimum number of additions per output sample (APOS).…”

Optimum multiplierless compensators for sharpened cascaded‐integrator‐comb decimation filters

“…Introduction: Multiplierless decimation filters are used as building blocks in high-speed multirate systems. Various methods for their design have been considered, resulting in the cascaded-integrator-comb (CIC) filter [1], sharpened CIC (SCIC) filters [2,3], and several filters obtained by modification of the original CIC response [4][5][6][7]. All filters referred to introduce passband droop, which is especially high for SCIC filters utilising folding-band sharpening.…”

“…However, we prefer the minimiser with c 0 > 0. This constraint is added to the constraints in (5). It simplifies the optimisation because with this constraint only a half of the coefficient space should be examined.…”