Efficient checker processor design

Chatterjee, S.; Weaver, Christopher; Austin, Todd

doi:10.1109/micro.2000.898061

Cited by 24 publications

(24 citation statements)

References 12 publications

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“…Prior work entrusts a robust checker to resolve input incoherence. For example, DIVA checkers with dedicated caches [8] and slipstreamed re-execution [25] both allow the leading thread's load values to differ from the trailing threads'. However, these proposals do not address the possibility of data races in shared-memory multiprocessors and require complex additions to support robust redundant execution.…”

Section: Input Incoherencementioning

confidence: 99%

Reunion: Complexity-Effective Multicore Redundancy

Smolens

Gold

Falsafi

et al. 2006

2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06)

114

110

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Section: Input Incoherencementioning

confidence: 99%

Reunion: Complexity-Effective Multicore Redundancy

Smolens

Gold

Falsafi

et al. 2006

2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06)

114

110

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“…We show that TRUSTNET and DATAWATCH protect the pipeline and cache memory systems for a microprocessor closely matching the Sun Microsystems' OpenSPARC T2 processor against a large class of attacks at the cost of negligible storage (less than 2 KB per core) and no performance loss. Additionally, TRUSTNET and DATAWATCH, in concert with pre-existing solutions (partial duplication [25]), can provide coverage against many known hardware design level backdoors.…”

Section: Tapeout and Fabrication Deploymentmentioning

confidence: 99%

Tamper Evident Microprocessors

Waksman

Sethumadhavan

2010

2010 IEEE Symposium on Security and Privacy

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Abstract-Most security mechanisms proposed to date unquestioningly place trust in microprocessor hardware. This trust, however, is misplaced and dangerous because microprocessors are vulnerable to insider attacks that can catastrophically compromise security, integrity and privacy of computer systems. In this paper, we describe several methods to strengthen the fundamental assumption about trust in microprocessors. By employing practical, lightweight attack detectors within a microprocessor, we show that it is possible to protect against malicious logic embedded in microprocessor hardware.We propose and evaluate two area-efficient hardware methods -TRUSTNET and DATAWATCH -that detect attacks on microprocessor hardware by knowledgeable, malicious insiders. Our mechanisms leverage the fact that multiple components within a microprocessor (e.g., fetch, decode pipeline stage etc.) must necessarily coordinate and communicate to execute even simple instructions, and that any attack on a microprocessor must cause erroneous communications between microarchitectural subcomponents used to build a processor. A key aspect of our solution is that TRUSTNET and DATAWATCH are themselves highly resilient to corruption. We demonstrate that under realistic assumptions, our solutions can protect pipelines and on-chip cache hierarchies at negligible area cost and with no performance impact. Combining TRUSTNET and DATAWATCH with prior work on fault detection has the potential to provide complete coverage against a large class of microprocessor attacks. 1Index Terms-hardware security, backdoors, microprocessors, security based on causal structure and division of work.

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“…The DIVA approach [19][20][21] uses a simple and robust processor, called DIVA checker, to verify the operation of the high-performance speculative core. This approach can also be adapted to support ILCOFT by selecting the instructions whose results have to be verified by the DIVA checker.…”

Section: Ft Schemes Adaptable To Ilcoftmentioning

confidence: 99%

Instruction-Level Fault Tolerance Configurability

Borodin

Juurlink

Hamdioui

et al. 2008

J Sign Process Syst Sign Image Video Technol

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Due to modern technology trends such as decreasing feature sizes and lower voltage levels, fault tolerance (FT) is becoming increasingly important in computing systems. Several schemes have been proposed to enable a user to configure the FT at the application level, thereby enabling the user to trade stronger FT for performance or vice versa. In this paper, we propose supporting instruction-level rather than application-level configurability of FT, since different parts of some applications (e.g., multimedia) can have different reliability requirements. Weak or no FT will be applied to less critical parts, resulting in time and/or resource gains. These gains can be used to apply stronger FT techniques to the more critical parts; hence increasing the overall reliability. The paper shows how some existing FT techniques can be adapted to support instruction-level FT configurability, how a programmer can specify the desired FT level of the instructions, and how the compiler can manage it automatically. A comparison between the existing FT scheme EDDI (which duplicates all instructions) and the proposed approach is performed both at the kernel and at full application levels. The simulation results show that both the performance and the energy consumption are significantly improved (up to 50% at the kernel and up to 16% at full application level), while the fault coverage depends on the application. For the full application (JPEG encoder), our approach is only applied to one kernel in order to avoid increasing the programming effort significantly.

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Efficient checker processor design

Cited by 24 publications

References 12 publications

Reunion: Complexity-Effective Multicore Redundancy

Reunion: Complexity-Effective Multicore Redundancy

Tamper Evident Microprocessors

Instruction-Level Fault Tolerance Configurability

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