Efficient area and power multiplication part of FFT based on twiddle factor decomposition

Abstract

This paper presents an efficient area and power multiplication part of radix-2 FFT (Fast Fourier Transform) architecture. The butterfly plays a central role in the FFT computation, and the multiplication part dominates its complexity. It is composed by a product of complex data and complex coefficients named twiddle factors. The proposed strategy consists on the decomposition of the real and imaginary coefficients of the twiddle factors into less complex ones, so that the multiplication part of the butterfly can be implemented with less area, what leads to the reduction of its power consumption. The strategy also includes the use of Constant Matrix Multiplication (CMM) and gate level approaches in the decomposed coefficients. A control unit is responsible for selecting the correct constant to be used after the decomposition. The proposed architectures were synthesized using SYNOPSYS Design Compiler and the UMC130nm technology. The results show that reductions of 10% in area and 8% in power could be achieved on average, when compared with state of the art solutions

New algorithm for design of low complexity twiddle factor multipliers in radix-2 FFT

“…The area cost of our design and the two competing designs are listed in Table V. Our design is about 31% lower than design by [7] and 4% lower than the design by [8]. This cost saving is contributed by the low cost ATEs searched in our algorithm.…”

“…The area costs of the designs by our algorithm, [7] and [8] are listed in Table V. Our design has achieved about 12% and 27% gate count saving over [7] and [8] respectively. Hence, the validity of the effectiveness of proposed cost metric in area reduction has been verified experimentally.…”

“…In this section, we will present the TFM designs by our proposed algorithm and compare with two most relevant designs by [7] and [8] to our best knowledge. 8-bit input signal x is assumed for the estimation of the bit widths of arithmetic operators.…”

“…8-bit input signal x is assumed for the estimation of the bit widths of arithmetic operators. The two-input adders are implemented with ripple carry adder, and some adders are implemented with carry save adder tree as illustrated in [7]. All designs in comparison are described in VHDL and synthesized by Mentor Graphics LeonardoSpectrum using 0.18µm standard cell library.…”

“…The generic multipliers in these designs are replaced by simpler arithmetic operators including adders and shifters to achieve lower hardware complexity, and the multiplexers are used to reconfigure the coefficient values. The works in [6] and [7] modelled the FFT complex multiplications as Multiple Constant Multiplication (MCM) problem where each input sample is multiplied with all possibly required constants required in FFT computation. Two multiplexers are employed in the last stage to select the desired products for real part and imaginary part respectively.…”