Efficient and retargetable SIMD translation in a dynamic binary translator

Abstract

The single-instruction multiple-data (SIMD) computing capability of modern processors is continually improved to deliver ever better performance and power efficiency. For example, Intel has increased SIMD register lengths from 128 bits in streaming SIMD extension to 512 bits in AVX-512. The ARM scalable vector extension supports SIMD register length up to 2048 bits and includes predicated instructions. However, SIMD instruction translation in dynamic binary translation has not received similar attention. For example, the widely used QEMU emulates guest SIMD instructions with a sequence of scalar instructions, even when the host machines have relevant SIMD instructions. This leaves significant potential for performance enhancement. We propose a newly designed SIMD translation framework for dynamic binary translation, which takes advantage of the host's SIMD capabilities. The proposed framework has been built in HQEMU, an enhanced QEMU with a separate thread for applying LLVM optimizations. The current prototype supports ARMv7, ARMv8, and IA32 guests on the X86-64 AVX-2 host. Compared with the scalar-translation version HQEMU, our framework runs up to 1.84 times faster on Standard Performance Evaluation Corporation 2006 CFP benchmarks and up to 6.81 times faster on selected real applications. FIGURE 3 The architecture of the hybrid QEMU framework. TCG, tiny code generation [Colour figure can be viewed at wileyonlinelibrary.com]

Lasagne: a static binary translator for weak memory model architectures

“…A number of static binary lifters target the LLVM IR [9,12,14,67,73] for analysis and transformation. Previous work provided correct translations for SIMD [24,25] or floating point instructions [25,75]. However, these translation tools do not support concurrency.…”

“…Crucially, the translation must preserve the semantics of the original binary, as specified by the original architecture, whilst also optimizing the target binary in a discernible way. Although SBT tools have gained popularity [24,25,74,75], their support of several advanced architectural features is often limited. For example, Microsoft's binary lifting prototype, called mctoll, was unable to lift the programs used in our evaluation.…”

Performance Improvements via Peephole Optimization in Dynamic Binary Translation

“…Cota et al [8] increased floating-point (FP) emulation performance by surrounding the use of host FP unit with a minimal amount of non-FP code. Spink et al [9] and Fu et al [10] translated guest SIMD instructions to host SIMD instructions, aiming to exploit ISA-specific features. Clark et al [11] proposed a register-mapping approach to reduce memory access and context switching overhead.…”