Efficient and low‐complexity hardware architecture of Gaussian normal basis multiplication over GF(2
            <i>
              <sup>m</sup>
            </i>
            ) for elliptic curve cryptosystems

Rashidi, Bahram; Sayedi, Sayed Masoud; Farashahi, Reza Rezaeian

doi:10.1049/iet-cds.2015.0337

Cited by 17 publications

(16 citation statements)

References 35 publications

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“…Reference [22] presents a lowarea and scalable digit-serial architecture to perform polynomial basis multiplications over Z 2 [x]. Two digit-serial architectures for multiplication over Galois fields employing the normal basis representation are presented in [23], [24]. By rewriting the multiplication equations in a normal basis form, the design in [23] can reduce both the hardware complexity and the combinational critical path.…”

Section: ) Hardware Acceleratorsmentioning

confidence: 99%

Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials

2020

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With the recent advances in quantum computing, code-based cryptography is foreseen to be one of the few mathematical solutions to design quantum resistant public-key cryptosystems. The binary polynomial multiplication dominates the computational time of the primitives in such cryptosystems, thus the design of efficient multipliers is crucial to optimize the performance of post-quantum public-key cryptographic solutions. This manuscript presents a flexible template architecture for the hardware implementation of large binary polynomial multipliers. The architecture combines the iterative application of the Karatsuba algorithm, to minimize the number of required partial products, with the Comba algorithm, used to optimize the schedule of their computations. In particular, the proposed multiplier architecture supports operands in the order of dozens of thousands of bits, and it offers a wide range of performance-resources trade-offs that is made independent from the size of the input operands. To demonstrate the effectiveness of our solution, we employed the nine configurations of the LEDAcrypt public-key cryptosystem as representative use cases for large-degree binary polynomial multiplications. For each configuration we showed that our template architecture can deliver a performance-optimized multiplier implementation for each FPGA of the Xilinx Artix-7 mid-range family. The experimental validation performed by implementing our multiplier for all the LEDAcrypt configurations on the Artix-7 12 and 200 FPGAs, i.e., the smallest and the largest devices of the Artix-7 family, demonstrated an average performance gain of 3.6x and 33.3x with respect to an optimized software implementation employing the gf2x C library.

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Section: ) Hardware Acceleratorsmentioning

confidence: 99%

Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials

2020

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“…In this work, design of field multiplier is based on our previously proposed efficient digit-serial GNB multiplier [20]. For the VLSI implementation, the structure of field multiplier is modified [21].…”

Section: Implementation Of the Digit-serial Gnb Multiplier Based On Lmentioning

confidence: 99%

“…The product C of the GNB multiplication based on

C_{1}

C_{2}

and

C_{3}

C = ()(, {()(, C_{1}^{2} + C_{2})}^{2} + C_{3}) .

The details of multiplication by

β

blocks and SIC blocks are given in [20].…”

Section: Implementation Of the Digit‐serial Gnb Multiplier Based On Lmentioning

confidence: 99%

“…In [20] the output signal of the multiplier is obtained from the output register, so one clock cycle is added to

w

and the number of clock cycles for each multiplication operation is w + 1. In this work, the place of this register is changed, and the output signal of multiplier is obtained from the final XOR gates outputs in the XOR tree.…”

Section: Implementation Of the Digit‐serial Gnb Multiplier Based On Lmentioning

confidence: 99%

“…(i) A full-custom efficient hardware structure for the point multiplication on BECs for ASIC applications. (ii) The PA and PD computations are scheduled by only one digitserial multiplier, and our previously reported digit-serial GNB multiplier [20,21] is used for implementation. In this multiplier, a structural very large-scale integration (VLSI) design of the XOR tree is presented based on logical effort technique and by using an optimised four-input XOR gate.…”

Section: Introductionmentioning

confidence: 99%

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Full‐custom hardware implementation of point multiplication on binary Edwards curves for application‐specific integrated circuit elliptic curve cryptosystem applications

Rashidi

Sayedi

Farashahi

2017

IET Circuits, Devices & Syst

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This study presents an efficient and high-speed very large-scale integration implementation of point multiplication on binary Edwards curves over binary finite field GF(2 m) with Gaussian normal basis representation. The proposed implementation is a low-cost structure constructed by one digit-serial multiplier. In the proposed scheduling of point multiplication, the field multiplier is busy during point addition and point doubling computations. In the field multiplier structure, by using the logical effort technique the delay is optimally decreased and the drive ability of the circuit in the point multiplication architecture is increased. Also, to reduce area and number of transistors of the point multiplication circuit, all components are selected based on low-cost structures. The design is implemented in 0.18 μm CMOS technology over binary finite field GF(2 233). The results confirm the validity of the proposed structure and its high performance in terms of delay and area cost.

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Efficient hardware implementations of point multiplication for binary Edwards curves

Rashidi

2018

Circuit Theory & Apps

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SummaryThis paper presents efficient and fast hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on extremely fast complete differential addition and doubling formulas. These new complete differential addition formulas are performed for general and special cases of BECs with cost of 5M + 4S + 2D and 5M + 4S + 1D, respectively, where, M, S, and D denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of the BECs, proposed structures are implemented based on 3 and 1 pipelined digit‐serial Gaussian normal basis multipliers. In the design by 3 multipliers, computation of point addition and point doubling is performed concurrently. But in the second implementation for low‐cost design with low number of hardware resources, these computations are implemented by 1 multiplier. Also, in the special case of BECs, 2 structures are proposed for achieving the highest degree of parallelization and utilization of resources by using 3 and 2 field multipliers. Implementation results of the proposed architectures based on Virtex‐5 XC5VLX110, Virtex‐4 XC4VLX100, and Arria‐10 10AX115U4F45I3SG FPGAs for 2 fields and are achieved. The results show improvements in terms of execution time, area, and efficiency for the proposed structures compared with previous works.

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Efficient and low‐complexity hardware architecture of Gaussian normal basis multiplication over GF(2 ^m ) for elliptic curve cryptosystems

Cited by 17 publications

References 35 publications

Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials

Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials

Full‐custom hardware implementation of point multiplication on binary Edwards curves for application‐specific integrated circuit elliptic curve cryptosystem applications

Efficient hardware implementations of point multiplication for binary Edwards curves

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Efficient and low‐complexity hardware architecture of Gaussian normal basis multiplication over GF(2 m ) for elliptic curve cryptosystems

Cited by 17 publications

References 35 publications

Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials

Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials

Full‐custom hardware implementation of point multiplication on binary Edwards curves for application‐specific integrated circuit elliptic curve cryptosystem applications

Efficient hardware implementations of point multiplication for binary Edwards curves

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Efficient and low‐complexity hardware architecture of Gaussian normal basis multiplication over GF(2 ^m ) for elliptic curve cryptosystems