Efficient algorithms for fast IR drop analysis exploiting locality

Köse, Selçuk; Friedman, Eby G.

doi:10.1016/j.vlsi.2011.09.003

Cited by 30 publications

(13 citation statements)

References 19 publications

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“…The two primary coupling mechanisms for switching noise are: 1) power and ground noise and 2) interconnect noise. Power and ground noise is caused by high-frequency switching of the instantaneous current, which introduces large current spikes that IR and inductive (Ldi /dt) voltage drops, producing voltage fluctuations in the power and ground distribution networks [33], [43]- [46]. Interconnect noise [47]- [49] or crosstalk is the voltage change induced on a victim node due to capacitive or inductive coupling from a switching node.…”

Section: A Signal Integrity Challenges In Deeply Scaled Cmosmentioning

confidence: 99%

Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS

Bai

Song

Bojnordi

et al. 2016

IEEE Trans. VLSI Syst.

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This paper explores the use of MOS current-mode logic (MCML) as a fast and low noise alternative to static CMOS circuits in microprocessors, thereby improving the performance, energy efficiency, and signal integrity of future computer systems. The power and ground noise generated by an MCML circuit is typically 10-100× smaller than the noise generated by a static CMOS circuit. Unlike static CMOS, whose dominant dynamic power is proportional to the frequency, MCML circuits dissipate a constant power independent of clock frequency. Although these traits make MCML highly energy efficient when operating at high speeds, the constant static power of MCML poses a challenge for a microarchitecture that operates at the modest clock rate and with a low activity factor. To address this challenge, a single-core microarchitecture for MCML is explored that exploits the C-slow retiming technique, and operates at a high frequency with low complexity to save energy. This design principle contrasts with the contemporary multicore design paradigm for static CMOS that relies on a large number of gates operating in parallel at the modest speeds. The proposed architecture generates 10-40× lower power and ground noise, and operates within 13% of the performance (i.e., 1/ExecutionTime) of a conventional, eight-core static CMOS processor while exhibiting 1.6× lower energy and 9% less area. Moreover, the operation of an MCML processor is robust under both systematic and random variations in transistor threshold voltage and effective channel length.Index Terms-Architecture-circuit codesign, energy efficient, low noise, microprocessors, MOS current-mode logic (MCML). 1063-8210

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Section: A Signal Integrity Challenges In Deeply Scaled Cmosmentioning

confidence: 99%

Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS

Bai

Song

Bojnordi

et al. 2016

IEEE Trans. VLSI Syst.

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“…(2) For P/G network analysis, according to the recently proposed closed-form expressions for voltage drops [35,36], we explore the relationships among the significant parameters that affect the voltage drops. Compared with the greedy method, we can obtain near-optimal solutions with much lower computational cost.…”

Section: Contributions Of the Proposed Approachmentioning

confidence: 99%

Efficient power pad assignment for multi‐voltage SoC and its application in floorplanning

Chu

Xia

Wang

et al. 2015

Circuit Theory & Apps

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Multi-voltage techniques are being developed to improve power savings by providing lower supply voltages for noncritical blocks under the performance constraint. However, the resulted lower voltage drop noise margin brings serious obstacles in power/ground (P/G) network design of the wire-bonding package. For voltage drop optimization, both block and power pad positions are important factors that need to be considered. Traditional multi-voltage floorplanning methods use rough estimation to evaluate the P/G network resource without considering the locations of power pads. To remedy this deficiency, in this paper, an efficient voltage drops aware power pad assignment (PPA) method is proposed, and it is further integrated into a floorplanning algorithm. We first present a fast PPA method for each power domain by the spring model. Then, to evaluate voltage drops during floorplanning iterations, the weighted distance from the blocks to the power pads is adopted as an optimization objective instead of time-consuming matrix computation. Experimental results on Gigascale System Research Center (GSRC) benchmark circuits indicate that the proposed method generates an optimized placement of power pads and floorplanning of blocks with high efficiency.decoupling capacitors configuration to alleviate the power delivery noise [12,13]. However, those techniques are implemented only when the floorplan or placement is ready. With exploding design complexity, it is necessary to consider voltage drop issues in the early design cycle [14][15][16][17]. Once the voltage drops aware floorplan is obtained, the detailed P/G network design can be performed in the subsequent placement and routing stages that consider Steiner tree construction and electromigration issues [18,19].It is reported that 5% of voltage decrease may cause the circuit performance slowdown up to 15% or more [20]. Hence, designers typically limit the voltage drops within 10% of the supply voltage to guarantee faultless operation [21]. Lower supply voltage indicates that lower noise margins or smaller voltage drops are permitted on the P/G network [22]. For instance, 1.5-V supply voltages permit 150-mV voltage drop while 1.0-V supply voltages only allow 100-mV voltage drop. Compared with single-voltage SoC, the voltage drop constraints present more challenges for the P/G network design of the multi-voltage SoC. First, from a low-power perspective, a VI with a larger area and a lower supply voltage is preferred during the VI generation process. However, the permitted ultra-low voltage drops make the P/G network hard to design. Second, power pads are located at the periphery of the chip for wire-bonding package. Locations of power pads affect both the timing and voltage drops [23]. Although multiple power pads for each VI can leverage the voltage drops, it may not be practical because the power pads must compete with other signal I/Os under the limited pad resource. Thus, it is vital to consider voltage drops in P/G network design for multi-voltage SoC. Related workConsid...

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“…Distributed on-chip voltage regulation is an emerging research area where multiple voltage regulators are connected in parallel, delivering current to the same power network close to the load circuits [3][4][5][6][7][8][9]. Switched capacitor (SC) and low dropout (LDO) voltage regulators are used for distributed voltage regulation due to the small size.…”

Section: Introductionmentioning

confidence: 99%

Thermal Implications of On-Chip Voltage Regulation

Köse

2014

Proceedings of the 51st Annual Design Automation Conference

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The primary objective of this paper is to investigate and evaluate the thermal implications of high power density onchip voltage regulators. This paper is a first attempt to highlight the importance of the number, size, and location of onchip voltage regulators on the thermal hotspots and thermal gradient. The physical location of on-chip voltage regulators is explored to distribute the hotspot locations and achieve spatial low pass filtering of the hotspots. A new thermalaware physical design and power management technique are proposed to spatially and temporally distribute the hotspot locations over the cooler areas within an integrated circuit. The proposed technique eliminates the thermal gradient due to on-chip voltage regulators without any performance loss.

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Efficient algorithms for fast IR drop analysis exploiting locality

Cited by 30 publications

References 19 publications

Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS

Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS

Efficient power pad assignment for multi‐voltage SoC and its application in floorplanning

Thermal Implications of On-Chip Voltage Regulation

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