Efficient algorithm and architecture for elliptic curve cryptography for extremely constrained secure applications

Azarderakhsh, Reza; Järvinen, Kimmo; Kermani, Mehran Mozaffari

doi:10.1109/tcsi.2013.2283691

Cited by 59 publications

(50 citation statements)

References 38 publications

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“…However, it did not give detail information about scalar multiplication execution time or frequency, so there is no way to compare the SM operation time with the proposed design here. The design in [18] adopts registers and bit-level multiplier share method and consumes 11.571 k gates area. The complexity of the scalar multiplication between GF(p) and GF(2 m ) is different, as example, the modular addition needs carry addition and modulo p operation in GF(p) while modular addition needs just xor operation in GF(2 m ).…”

Section: Implementation and Resultsmentioning

confidence: 99%

“…The modular addition is fundamental operation in low area ECC architecture. Therefore is difficult to compare which are better among [17,18] and the proposed design here from area consumption and operation time. Table 6 shows the performance data of several existing FPGA implementations based on EC scalar multiplication.…”

Section: Implementation and Resultsmentioning

confidence: 99%

“…Many hardware implementations of ECC have been proposed [6][7][8][9][10][11][12][13][14][15][16][17][18] for ECC. The accelerator of modular multiplication (MM) can be divided into two categories: multiplier-based architecture and adder-based architectures.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Low Hardware Consumption Elliptic Curve Cryptographic Architecture over GF(p) in Embedded Application

Zheng

Zhang

et al. 2018

Electronics

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Abstract:In this paper, a low hardware consumption design of elliptic curve cryptography (ECC) over GF(p) in embedded applications is proposed. The adder-based architecture is explored to reduce the hardware consumption of performing scalar multiplication (SM). The Interleaved Modular Multiplication Algorithm and Binary Modular Inversion Algorithm are improved and implemented with two full-word adder units. The full-word register units for data storage are also optimized. The design is based on two full-word adder units and twelve full-word register units of pipeline structure and was implemented on Xilinx Virtex-4 platform. Design Compiler is used to synthesized the proposed architecture with 0.13 µm CMOS standard cell library. For 160, 192, 224, 256 field order, the proposed architecture consumes 5595, 7080, 8423, 9370 slices, respectively, and saves 17.58∼54.93% slice resources on FPGA platform when compared with other design architectures. The synthesized result uses 35.43 k, 43.37 k, 50.38 k, 57.05 k gate area and saves 52.56∼91.34% in terms of gate count in comparison. The design takes 2.56∼4.07 ms to perform SM operation over different field order under 150 MHz frequency. The proposed architecture is safe from simple power analysis (SPA). Thus, it is a good choice for embedded applications.

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Section: Implementation and Resultsmentioning

confidence: 99%

Section: Implementation and Resultsmentioning

confidence: 99%

See 1 more Smart Citation

A Low Hardware Consumption Elliptic Curve Cryptographic Architecture over GF(p) in Embedded Application

Zheng

Zhang

et al. 2018

Electronics

View full text Add to dashboard Cite

show abstract

“…The estimated total number of NAND gates equivalent (GE) is 12,102 from the synthesized results, and a maximum clock frequency is 800 MHz. However, we use a clock frequency of 1,130 KHz in order to compare with other works [15][16][17]. As can be seen, the proposed architecture uses a similar number of NAND gates compared to other works.…”

Section: Results and Comparisonmentioning

confidence: 99%

Efficient Algorithm and Architecture for Elliptic Curve Cryptographic Processor

Tan¹,

Lee

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.

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“…When compared to stateof-the-art implementations, their implemented design achieved higher speeds and better area-delay. Kimmo U. Järvinen et.al [16] suggested efficient algorithm and architecture for elliptic curve cryptography for extremely constrained secure applications. They proposed an efficient implementation of point multiplication on Koblitz curves targeting extremely-constrained, secure applications.…”

Section: Related Workmentioning

confidence: 99%