Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective

Packirisamy, Venkatesan; Luo, Yangchun; Hung, W. L.; Zhai, Antonia; Yew, Pen-Chung; Ngai, Tin-Fook

doi:10.1109/iccd.2008.4751875

Cited by 10 publications

(5 citation statements)

References 18 publications

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“…Packirisamy et al [2008] compared and contrasted the energy efficiency of SMT and CMP in terms of supporting TLS workload under the same die area constraints. They examined how the interactions between speculative threads affect their energy efficiency in SMT-mode and CMP-mode execution.…”

Section: Related Workmentioning

confidence: 99%

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The design and implementation of heterogeneous multicore systems for energy-efficient speculative thread execution

Luo

Hsu

Zhai

2013

ACM Trans. Archit. Code Optim.

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With the emergence of multicore processors, various aggressive execution models have been proposed to exploit fine-grained thread-level parallelism, taking advantage of the fast on-chip interconnection communication. However, the aggressive nature of these execution models often leads to excessive energy consumption incommensurate to execution time reduction. In the context of Thread-Level Speculation, we demonstrated that on a same-ISA heterogeneous multicore system, by dynamically deciding how on-chip resources are utilized, speculative threads can achieve performance gain in an energy-efficient way.Through a systematic design space exploration, we built a multicore architecture that integrates heterogeneous components of processing cores and first-level caches. To cope with processor reconfiguration overheads, we introduced runtime mechanisms to mitigate their impacts. To match program execution with the most energy-efficient processor configuration, the system was equipped with a dynamic resource allocation scheme that characterizes program behaviors using novel processor counters.We evaluated the proposed heterogeneous system with a diverse set of benchmark programs from SPEC CPU2000 and CPU20006 suites. Compared to the most efficient homogeneous TLS implementation, we achieved similar performance but consumed 18% less energy. Compared to the most efficient homogeneous uniprocessor running sequential programs, we improved performance by 29% and reduced energy consumption by 3.6%, which is a 42% improvement in energy-delay-squared product.

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Section: Related Workmentioning

confidence: 99%

“…Previous work has shown that SMT and CMP could result in different levels of energy efficiency [Packirisamy et al 2008]. Thus, we explore the possibility for both types of multithreading support.…”

Section: Introductionmentioning

confidence: 99%

The design and implementation of heterogeneous multicore systems for energy-efficient speculative thread execution

Luo

Hsu

Zhai

2013

ACM Trans. Archit. Code Optim.

Self Cite

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“…Although EPIC processors are statically scheduled, they require extensive software/hardware assistance to provide the processor with information to deal with events such as branch prediction, load speculation, and necessary exception handling. As a result EPIC architectures require mechanisms to communicate this parallelism to its underlying hardware [45].…”

Section: Explicitly Parallel Instruction Processors (Epic)mentioning

confidence: 99%

Configurable simultaneously single-threaded (multi-)engine processor

Tino¹

2021

Preprint

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As the multi-core computing era continues to progress, the need to increase single- thread performance, throughput, and seemingly adapt to thread-level parallelism (TLP) remain important issues. Though the number of cores on each processor continues to increase, expected performance gains have lagged. Accordingly, com- puting systems often include Simultaneously Multi-Threaded (SMT) processors as a compromise between sequential and parallel performance on a single core. These processors effectively improve the throughput and utilization of a core, however often at the expense of single-thread performance as threads per core scale. Accordingly, applications which require higher single-thread performance must often resort to single-thread core multi-processor systems which incur additional area overhead and power dissipation. In attempts to improve single- and multi-thread core efficiency, this work introduces the concept of a Configurable Simultaneously Single-Threaded (Multi-)Engine Processor (ConSSTEP). ConSSTEP is a nuanced approach to multi- threaded processors, achieving performance gains and energy efficiency by invoking low overhead reconfigurable properties with full software compatibility. Experimen- tal results demonstrate that ConSSTEP is able to increase single-thread Instruc- tions Per Cycle (IPC) up to 1.39x and 2.4x for 2-thread and 4-thread workloads, respectively, improving throughput and providing up to 2x energy efficiency when compared to a conventional SMT processor.

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“…[Packirisamy et al 2008;Tang et al 2005] compared SMT with CMP (Chip Multiprocessors) in the context of TLS, giving a perspective of performance, power and thermal;[Ungerer et al 2003] described chips that support multithreading. However, a full description of these processors is beyond the scope of this survey, and will not be provided.…”

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confidence: 99%