Efficiency Comparison between Doubler and Dickson Charge Pumps

High-Efficiency Regulated Charge Pump for Non-Volatile Memories

“…The supply voltage V DD and the required output voltage V D were 1.2 V and 4.5 V, respectively, and the maximum load current I L was 2 mA (C L = 50 pF, C DEC = 150 pF and R 1 = 100 kΩ, R 2 = 800 kΩ for V ref = 0.5 V). In both approaches, a 4-stage charge pump based on the voltage doubler topology operating at a frequency f of 50 MHz was chosen (indeed, the voltage doubler topology inherently has better power efficiency as compared to Dickson scheme [6]). …”

DC–DC converter for fuel-cells and portable devices in digital CMOS technology

“…As for the series switch of the boost converter, using NMOS device is preferred for minimizing the series resistance, impacting the converter efficiency. Indeed, NMOS transistors outperform PMOS devices in the Dickson converter if a boot-strapped gate control is introduced in order to drive the series transistor with the maximum gate-to-source voltage [8].…”

“…Considering the low input voltage and the efficiency requirements the series switches are boot-strapped NMOS transistors. Through a switchedcapacitor circuit the gate-source voltage is boot-strapped to the swing of the clock waveform, thus leading to the minimum achievable series resistance [8]. In order to relax the design of the boot-strapped control of the switch connected to the load, M 5 , a PMOS device was used, driven by a clock waveform with a swing comparable to the converter output (5 V).…”

“…It is worth noticing the gate voltage of M 2 may reach 3.6 V. Considering the relevant gate capacitance of the series device, an external capacitor was used, C B , in order to limit the silicon area and the reduction of the available gate-source voltage due to the charge sharing effect. In order to maximize the converter efficiency and limit the chip area, gate boosting is also implemented in the 3x SC converter [8]. The auxiliary external capacitors have a negligible impact on the cost of the systems, considering the COB mounting (thus relaxing the constraint on the maximum pin number) and the low cost impact of the SMD ceramic capacitors.…”

A discussion on exponential-gain charge pump

“…Another very popular CP scheme is based on the voltage doubler topology [6], which is able to achieve better power efficiency as compared to Dickson CP [9]. A limit of both the above schemes is inherently related to their topology, as the achievable voltage gain linearly increases with the number n of stages (to be specific, the voltage gain under ideal conditions, i.e, neglecting parasitics, is given by G = n + 1).…”