Efficiency and reliability enhancement of silicon nanocrystal field-effect luminescence from nitride-oxide gate stacks

Abstract

We report on a field-effect light emitting device based on silicon nanocrystals in silicon oxide deposited by plasma-enhanced chemical vapor deposition. The device shows high power efficiency and long lifetime. The power efficiency is enhanced up to ϳ0.1% by the presence of a silicon nitride control layer. The leakage current reduction induced by this nitride buffer effectively increases the power efficiency two orders of magnitude with regard to similarly processed devices with solely oxide. In addition, the nitride cools down the electrons that reach the polycrystalline silicon gate lowering the formation of defects, which significantly reduces the device degradation. © 2008 American Institute of Physics. ͓DOI: 10.1063/1.2939562͔The materials based on silicon nanocrystals ͑Si-ncs͒ are attractive for a wide variety of electronic and optoelectronic applications thanks to their tunable emission in the visible range and their compatibility with mainstream complementary metal oxide semiconductor ͑MOS͒ technology. [1][2][3][4][5][6] In the last years, an increasing number of articles dealing with electroluminescence ͑EL͒ from Si-nc embedded in silicon oxide ͑Si-nc/ SiO 2 ͒ devices has been published. Many of them report emission under direct current ͑dc͒ polarization, 7-9 which usually leads to low emission efficiency and fast degradation. Other authors report emission under alternate current ͑ac͒ polarization, 3,10,11 applying the concept of field-effect luminescence, where the recombination takes place after the sequential injection from the substrate of electrons and holes. The alternate injection can be adjusted to a suitable duty cycle which optimizes not only the current flow but also the polarization stress and the device lifetime. In spite of this, the leakage current is still very high and, also in this case, leads to low power efficiencies. 10 Therefore, the reduction of the leakage current appears to be a key issue for the achievement of an efficient device. In this challenge, the addition of a thin silicon nitride ͑Si 3 N 4 ͒ layer in a typical metal nitrideoxide semiconductor ͑MNOS͒ configuration is presented as a promising solution. [12][13][14] The MNOS stack reduces the effective field in the oxide layer, lowering the current flow that, in MOS configurations, is strongly field dependent ͓Fowler-Nordheim ͑FN͔͒. 15 The additional nitride barrier hinders the gate injection without significantly affecting the injection from the substrate, thus enhancing the power efficiency, as will be demonstrated later on. Thanks to the thinness of the Si 3 N 4 buffer and to its relatively high dielectric constant, the overall thickness increase does not have a remarkable impact on the gate voltage. The device lifetime improves as the nitride matrix cools down the carriers from the oxide, reducing the damage generated at the polycrystalline silicon ͑top contact͒ interface.In the present work, we demonstrate a twofold improvement through the addition of a thin Si 3 N 4 control layer within the MOS stack. First, we show ...

Si-nanocrystal-based LEDs fabricated by ion implantation and plasma-enhanced chemical vapour deposition

“…In the case of the MNOS structure, the nitride buffer reduces the device leakage current leading to a better profit of the injected charge that translates into power efficiencies of about 1% and output emission powers of ∼10 nW. It is worth noting the slow variation of the power efficiency with the gate bias in MNOS structures that is attributed to the increase of the FN onset [34].…”

“…The weak emission of sample PD5 is, in contrast to samples PD2 and PD3, associated to the loss of quantum confinement and to the emergence of carrier migration phenomena. Figure 21(c) compares the power efficiency of different deposited and implanted samples to the values obtained from a reference device, with a MNOS (metal nitride oxide semiconductor) configuration that has been recently reported as a highefficiency structure [34]. A thin buffer of pure Si 3 N 4 (∼15 nm) is deposited onto the SRO in order to limit the device leakage current.…”

“…A thin buffer of pure Si 3 N 4 (∼15 nm) is deposited onto the SRO in order to limit the device leakage current. More details about this kind of structures can be found in reference [34]. The values depicted in figure 21(c) are calculated by adjusting the gate voltage to its optimum frequency and under the assumption that the emission pattern of these devices is approximately Lambertian.…”

Luminescent Devices Based on Silicon-Rich Dielectric Materials

“…In previous studies, it has been reported that the combination of Si 3 N 4 /SRO structure improves luminescent emission properties [73,74]. Previous studies have also shown that a Si 3 N 4 -SRO bilayer structure improves the operation of light-emiting devices, such as a reduced leakage current, a reduced electric ield on the oxide layer, and results an improvement in eiciency and a longer device life [73][74][75][76].…”

“…Previous studies have also shown that a Si 3 N 4 -SRO bilayer structure improves the operation of light-emiting devices, such as a reduced leakage current, a reduced electric ield on the oxide layer, and results an improvement in eiciency and a longer device life [73][74][75][76]. In this chapter, the efect of a SRN ilm on a SRO ilm (SRN/SRO bilayers) on their optical properties is analyzed.…”