Efficiency and linearity improvement in power amplifiers for wireless communications

Asbeck, P.M.; Hannington, G.; Chen, P.F.; Larson, L.E.

doi:10.1109/gaas.1998.722610

Cited by 23 publications

(6 citation statements)

References 2 publications

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“…Average efficiency is calculated based on the probability of the PA transmitting at each output power level, as given in [3], and the converter state as a function of the PA's RF output power, which has been defined for the overall circuit architecture. Simulations were also performed to evaluate the effects of changes in the load current, which was simulated by changing the load resistance.…”

Section: Figure 7 Efficiency Versus Output Currentmentioning

confidence: 99%

“…Typical wireless device power amplifiers provide efficiencies on the order of 30-40% at maximum power output levels; however they do not operate at these levels the vast majority of the time and as such their average efficiency is much lower, as shown in Figure 1. Since the full supply voltage is not required for lower RF power output levels, it has been shown that this average efficiency (and hence battery lifetime) can be dramatically improved by decreasing the supply voltage of the PA when large output power levels are not required, decreasing the DC power draw [3,6].…”

Section: Introductionmentioning

confidence: 99%

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Integrated DC-DC converter design for improved WCDMA power amplifier efficiency in SiGe BiCMOS technology

Guckenberger

Kornegay

2003

Proceedings of the 2003 International Symposium on Low Power Electronics and Design - ISLPED '03

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We present a DC-DC converter design for on-chip integration with a WCDMA power amplifier to provide supply voltage modulation and efficiency enhancement. It operates from a 3.3V supply using 0.35µm 'high-breakdown' CMOS transistors available in IBM's SiGe BiCMOS 6HP process. Five selectable output voltage levels are available ranging from 1.3V to 3.3V. The converter is optimized for operation at 88.7MHz. Simulation results show an average efficiency of 78.8% over power amplifier operating conditions and a peak enabled efficiency of 86%. CCM-DCM mode switching and transistor width switching are used to minimize losses at the different output voltage and current load levels.

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Section: Figure 7 Efficiency Versus Output Currentmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Integrated DC-DC converter design for improved WCDMA power amplifier efficiency in SiGe BiCMOS technology

Guckenberger

Kornegay

2003

Proceedings of the 2003 International Symposium on Low Power Electronics and Design - ISLPED '03

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“…The overall characteristics of the implemented converter are summarized in Table 4. Average efficiency is calculated based on the probability of the PA transmitting at each output power level, as given in [3], and the converter state as a function of the PA's RF output power, which has been defined for the overall circuit architecture. Simulations were also performed to evaluate the effects of changes in the load current, which was simulated by changing the load resistance.…”

Section: Figure 7 Efficiency Versus Output Currentmentioning

confidence: 99%

Integrated DC-DC converter design for improved WCDMA power amplifier efficiency in SiGe BiCMOS technology

Guckenberger¹,

Kornegay²

2003

Proceedings of the 2003 International Symposium on Low Power Electronics and Design - ISLPED '03

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“…To improve efficiency, the supply voltage tracks the envelope level to minimise the DC bias power of the power transistor. The gate (or base) bias is used to maintain constant gain, which improves or restores the intermodulation performance [14]. High efficiency switching mode amplitude modulators are used to modulate the supply voltage, and linear techniques can be used for the gate (or base) bias due to the lower power.…”

Section: Dynamic Bias Techniquesmentioning

confidence: 99%

Increasing the talk-time of mobile radios with efficient linear transmitter architectures

Mann

Beach

Warr

et al. 2001

Electronics &Amp; Communication Engineering Journal

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In order to meet the linearity specification of standards such as GSM EDGE and TETRA the power amplifier (PA) linearisation methods in common usage today result in low DC to RF efficiency (e.g. Cartesian loop and adaptive predistortion). The transmitter places a heavy demand on the battery and therefore utilising more efficient transmitters can increase talk-time or reduce the battery size. For GSM EDGE and TETRA modulation it is shown that to obtain a transmitter efficiency (of >50%) the PA needs to be biased as class-C. The effect power amplifier efficiency has on talk-time is demonstrated for a handportable with fixed power overhead owing to the digital processing required to compile and transmit a burst or packet. It is shown that the PA efficiency for a transmitter operating backed-off (under power control), has a marginal impact on the talk-time and that the effect is largest at high output powers. This is put in context by a review of the various linearisation schemes such as Cartesian loop, polar loop, 2 nd harmonic injection, envelope elimination & restoration (EER), predistortion methods, and synthesis techniques (e.g. LINC & CALLUM). The review also discusses which methods are not suitable for handportable design, and documents the strengths and weaknesses of the remaining methods. The paper shows that to increase the power efficiency (and thus talk-time), hybrid solutions to power amplifier linearisation are required. Finally, existing hybrid solutions and their shortfalls are discussed.

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Efficiency and linearity improvement in power amplifiers for wireless communications

Cited by 23 publications

References 2 publications

Integrated DC-DC converter design for improved WCDMA power amplifier efficiency in SiGe BiCMOS technology

Integrated DC-DC converter design for improved WCDMA power amplifier efficiency in SiGe BiCMOS technology

Integrated DC-DC converter design for improved WCDMA power amplifier efficiency in SiGe BiCMOS technology

Increasing the talk-time of mobile radios with efficient linear transmitter architectures

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