Effects of the presence/absence of HCl during gate oxidation on the electrical and structural properties of polycrystalline silicon thin-film transistors

Abstract

The influence of the presence or absence of HCl during gate oxidation at 1100 and 1150 °C on the electrical and structural properties of polycrystalline silicon thin-film transistors was investigated. Devices processed without HCl exhibited a lower leakage current, a larger current switching ratio, a 25%–55% increase in carrier mobility, and a 21%–30% lower grain-boundary trap density. Materials investigation showed that the improvement was not primarily due to an increase in grain size, which was about 1000 Å irrespective of processing conditions, but to a change in crystallite orientation. X-ray diffraction measurements showed an increased {110} texture in devices processed without HCl. In addition, in the latter devices, dopant diffusion under the gate from the source and drain contacts was reduced by 7.6% to 12%. A linear relationship was observed between the average grain-boundary trap density and the average lateral dopant diffusion length. These findings are explained by considering the point defect chemistry and its relationship to grain-boundary mobility. Removal of HCl from the oxidation ambient increases the concentration of silicon self-interstitials. The increased migration of these point defects to grain boundaries enhances their nonconservative motion and therefore increases grain-boundary mobility. This in turn, allows the boundary to more completely acquire a lower-energy configuration. This lower-energy configuration of the boundary contains a minimum of broken bonds and therefore minimizes both the grain-boundary electrical activity and the diffusion along grain boundaries.

Conduction and low-frequency noise in high temperature processed polycrystalline silicon thin film transistors

“…In addition, since dopant diffusion in a polycrystalline material is enhanced by the preferential diffusion along grain boundaries, diffusion from the source and drain contacts in polysilicon TFTs during the activation anneal can substantially reduce the effective channel length. 4 Such a channel length reduction induce significant error in the analysis of the noise data. For this reason, in the measured polysilicon TFTs, the effective channel length is also required.…”

“…Such hightemperature processes have already been used for investigation of polysilicon/SiO 2 structures. 4,5 In this article, we present conduction and channel noise measurements on high-temperature processed polysilicon TFTs. The purpose of this study is to investigate the effects of boron and phosphorus doping as well as of the hydrogen grain boundary trap states passivation on: ͑a͒ The characteristics of the polysilicon TFTs in terms of the variations of the device parameters including the field-effect mobility and the threshold voltage and ͑b͒ on the change in the grain boundary trap-state density.…”

High-Performance Polycrystalline Silicon Thin-Film Transistors Based on Metal-Induced Crystallization in an Oxidizing Atmosphere

“…The extracted field-effect mobility of the Sample B is increased by 28%. The improvement of the TFT performance for the Sample B is attributed to the oxidizing annealing process, during which a thin SiO 2 layer is thermally grown on the surface of the poly-Si layer and silicon interstitials are generated and injected [9]. When the surface of silicon is oxidized, a volume expansion occurs and induces stress.…”

A Simple Method to Grow Thermal <inline-formula> <tex-math notation="TeX">${\rm SiO}_{2}$ </tex-math></inline-formula> Interlayer for High-Performance SPC Poly-Si TFTs Using <inline-formula> <tex-math notation="TeX">${\rm Al}_{2}{\rm O}_{3}$ </tex-math></inline-formula> Gate Dielectric

“…Also due to the improved interface quality, the interface trapassisted tunneling [14] may be greatly alleviated, resulting in significant improvement in GIDL current. On the other hand, when oxidizing the poly-Si film, excess Si interstitials generated at and migrated from the oxidizing interface would modify the GBs at the surface of poly-Si film by facilitating the climb of intrinsic GB dislocations and therefore result in lower trap state density (N t ) [15] and improved μ F E , V th and SS [13]. The GB N t could be estimated by using Proano and Levinson method [16], [17] at low source-drain voltage and Table I, the GB N t of TFT with and without interlayer are calculated as 4.98 × 10 12 cm −2 and 5.52 × 10 12 cm −2 respectively, implying the GBs is indeed improved when performing the oxidation of poly-Si film.…”