Effects of Long-Time Current Annealing to the Hysteresis in CVD Graphene on SiO2

Abstract

Graphene specimens produced by chemical vapor deposition usually show p-type characteristics and significant hysteresis in ambient conditions. Among many methods, current annealing appears to be a better way of cleaning the sample due to the possibility of in-situ annealing in the measurement setup. However, long-time current annealing could increase defects in the underlying substrate. Studying the hysteresis with different anneal currents in a graphene device is, therefore, a topic of interest. In this experimental work, we investigate electron/hole transport in a graphene sample in the form of a Hall bar device with a back gate, where the graphene was prepared using chemical vapor deposition on copper foils. We study the hysteresis before and after current annealing the sample by cooling down to a temperature of 35 Kfrom room temperature with a back-gate bias in a closed cycle refrigerator.

Study of graphene p-n junctions formed by the electrostatic modification of the SiO2 substrate

“…Yu et al 18 also reported the formation of p-n junction in graphene via this electrical stressing-voltage-method and they reported that mobility improvement is realized by reducing the impurity induced scattering in graphene as a result of low level stressing voltage 18 . Therefore, this stressing-voltage-technique has also been applied to improve the quality of graphene based devices 19 , 20 .…”