Effects of Localized Back-Surface Defects on Bulk and Front-Channel Conduction of Amorphous InGaZnO TFTs

Hsu, Chih-Chieh; Chen, Heping; Wang, Siang-Yu

doi:10.1109/ted.2015.2502277

Cited by 4 publications

(1 citation statement)

References 35 publications

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“…They function as switching and driving transistors in pixel circuits. Panels with a fast response time and a high resolution are required to meet the increasing demands for functionality and diversity of displays, such as ultra-high resolution and virtual reality applications [1][2][3][4]. In this situation, investigation of high-mobility TFTs is critical.…”

Section: Introductionmentioning

confidence: 99%

Performance dependence of self-aligned dual-gate poly-Si TFTs on localized defective regions

Hsu¹,

Li²,

Chen³

et al. 2020

Semicond. Sci. Technol.

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This study investigates effects of localized defect regions on electrical characteristics of self-aligned dual-gate poly-Si thin-film transistors (TFTs). The thickness of the poly-Si channel layer ranges from 20 nm to 140 nm. The threshold voltage, subthreshold swing, and mobility are found to be sensitive to the defect position. The localized defects in the left channel (source side) exhibit a significant impact while those in the right channel (drain side) show a lower influence on the TFT performance. In addition, the performance variation caused by the localized defects in the right channel is highly sensitive to the magnitude of the applied drain bias. A higher drain bias can observably reduce the performance degradation. Effects of multiple defect regions on the electrical behavior of the TFTs are also explored. We found that the upper width of the defect regions dominates the TFT performance deterioration. The hole transport, hole concentration distributions, and current flowlines are analyzed to study the physical mechanisms.

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Section: Introductionmentioning

confidence: 99%