Effects of Intermittent Faults on the Reliability of a Reduced Instruction Set Computing (RISC) Microprocessor

Abstract

Gracia-Morán, J.; Baraza Calvo, JC.; Gil Tomás, DA.; Saiz-Adalid, L.; Gil, P. (2014 > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1Abstract-With the scaling of CMOS technology to the submicron range, designers have to deal with a growing number and variety of fault types. In this way, intermittent faults are gaining importance in modern VLSI circuits. The presence of these faults is increasing due to the complexity of manufacturing processes (which produce residues and parameter variations), together with special aging mechanisms. This work presents a case study of the impact of intermittent faults on the behavior of a RISC microprocessor. We have carried out an exhaustive reliability assessment by using VHDL-based fault injection. In this way, we have been able to modify different intermittent fault parameters, to select various targets, and even, to compare the impact of intermittent faults with those induced by transient and permanent faults.

Low cost error monitoring for improved maintainability of IoT applications

“…Systematic erroneous behaviour (SEB) is defined as the event in which, for a particular workload size S, systematic errors occur at a high enough rate, that the online signal probability of an output falls outside the signature window w. SEB may occur in-the-field due to intermittent faults caused by defects escaping manufacturing testing, process variation, wearout and aging [8]. Intermittent faults may manifest as multiple bit-flips or exhibit a behaviour similar to permanent faults under specific operating conditions [9].…”

“…The evaluation of this technique was performed for errors induced by stuck-at faults and multiple bit-flips, as these error models produce a behaviour similar to that of long duration intermittent faults occurring in-the-field [8], [9]. Unbiased workloads of different sizes of uncorrelated random patterns were applied during simulations.…”

Low power probabilistic online monitoring of systematic erroneous behaviour

“…Intermittent faults at circuits manufactured using Very Deep Sub-Micron (VDSM) technologies manifest as bursts of errors that repeat periodically at the same places [1], causing the circuit to exhibit systematic erroneous behaviour (SEB). Devices in the field that exhibit SEB must be identified and maintained.…”

“…are dependent on the input signal probabilities. Systematic erroneous behaviour (SEB) is defined as the event in which, for a particular workload size S, systematic errors occur at a high enough rate that the OSP of an output falls outside the signature window w. SEB may occur in-the-field due to intermittent faults that manifest periodically as multiple bit-flips or exhibit a behaviour similar to permanent faults under specific operating conditions [1]. When such a fault is activated, it may generate enough errors that the OSP falls outside the signature window bounds.…”

“…Figures 2b and 2c present the histograms of OSP for faults and errors, respectively, after performing a full single stuck-at (SSA) fault injection campaign. The SSA fault model is used to emulate intermittent faults causing [1]. The horizontal axis shows the OSP and the vertical axis shows the number of injected faults that exhibit the corresponding OSP.…”