Effects of gate insulator using high pressure annealing on the characteristics of solid phase crystallized polycrystalline silicon thin-film transistors

Abstract

The oxidizing ambient was built using high pressure H2O vapor at 550 °C. For the solid phase crystallization (SPC) polycrystalline silicon (poly-Si) that is annealed for 1 h at 2 MPa, the oxide thickness is about 150 Å. The oxide layer is approximately 90 Å above the original surface of the poly-Si and 60 Å below the original surface. The oxide layer is used as the first gate insulator layer of thin-film transistors (TFTs). The heating at 550 °C with 2 MPa H2O vapor increased the carrier mobility from 17.6 cm2/V s of the conventional SPC process to 30.4 cm2/V s, and it reduced the absolute value of the threshold voltage (Vth) from 4.13 to 3.62 V. The subthreshold swing also decreased from 0.72 to 0.60 V/decade. This improvement is attributed mainly to the reduction in defect density at the oxide/poly-Si interface and in the poly-Si film by the high pressure annealing (HPA) process. Since the realization of excellent performance at the oxide/poly-Si interface and in poly-Si depends on the defect density, the poly-Si having the thermal oxide formed by a combined process of SPC and HPA may be well suited for fabrication of poly-Si TFTs for flat panel displays such as active matrix organic light emitting diodes.

High Mobility P-Channel Thin-Film Transistors with Ultralarge-Grain Polycrystalline Silicon Formed Using Nickel-Induced Crystallization

“…In the ULG poly-Si TFTs, the results showed a low V TH compared with other p-channel TFTs formed by MIC or SPC methods, which is even comparable to TFTs that of formed by the ELA method. [25][26][27] In a previous research, V TH was calculated using the following equation: 28)…”

Effects of the single and double (overlap) scanned excimer laser annealing on solid phase crystallized silicon films

“…In particular, the gate voltage swing (S factor), which represents the defect states at interface between the gate insulator and poly-Si layer in TFT, is typically sensitive to the defect density at the interface. For the completely depleted TFTs, in which the contained trap state density is related to defects, the S factor can by expressed as [8] S ¼ kT q ln 10 1 þ…”

High Performance Printed Ultraviolet-Sensors Based on Indium–Tin-Oxide Nanocrystals

“…17) Oxygen vacancies are generated at high partial pressure and high temperature. Therefore, annealing under external pressure is a possible way to reduce the formation of vacancies, and several studies have tested this approach on various materials, [18][19][20] revealing that highpressure annealing (>GPa) suppresses the increase of anion vacancies in films such as ZnO and GaN. 21,22) These previous findings suggest that pressurized annealing could also improve the performance of ITO-based thin films and printed ITO layers.…”